Semiconductor integrated circuit comprising bipolar transistors and MOS transistors and associated fabrication method

Claim 1

A semiconductor integrated circuit apparatus comprising: (a) a bipolar transistor formed on a substrate of semiconductor material; (b) a MOS transistor formed on said semiconductor substrate; said bipolar transistor including: (a-1) a base extraction electrode; said base extraction electrode being associated with a graft base region around a base region; said base extraction electrode being overlaid with a first insulator layer, and having at a side-surface thereof a first side-wall layer; (a-2) an emitter region; said emitter region being formed in a manner of self-alignment with said first side-wall layer; (a-3) an emitter extraction electrode; said MOS transistor including: (b-1) a gate electrode; said gate electrode being overlaid with a second insulator layer, and having at a side-surface thereof a second side-wall layer; (b-2) a source-drain region; said source-drain region being formed in a manner of self-alignment with said second side-wall layer; wherein: said first side-wall layer is formed by lamination of a third insulator layer formed on the side-surface of said base extraction electrode and a conductor layer overlying said third insulator layer; said second side-wall layer is composed of a fourth insulator layer that is formed together with said third insulator layer in a single fabrication step.

Claim 7

A method of fabricating a semiconductor integrated circuit apparatus composed of a bipolar transistor and a MOS transistor formed on a single semiconductor substrate, said method comprising the steps of: (a) forming over said semiconductor substrate an isolation layer for insulating said bipolar transistor and said MOS transistor, and forming a gate insulator layer over device regions excluding the region where said isolation layer has already been formed; (b) performing an etching process step to strip said gate insulator layer from a region where said bipolar transistor is formed, and depositing a first conductor layer and a first insulator layer over the entirety of said semiconductor substrate; (c) subjecting said first insulator layer and said first conductor layer to an etching process step to form a base extraction electrode for said bipolar transistor, an insulator layer on top of said base extraction electrode, a gate electrode for said MOS transistor, and an insulator layer on top of said gate electrode; (d) forming a second insulator layer on a side-surface of said base extraction electrode, on top of an emitter formation region surrounded by said base extraction electrode, and on a side-surface of said gate electrode, and depositing on the entirety of said semiconductor substrate a third insulator layer and a second conductor layer; (e) subjecting said second conductor layer to an etching process step to form on the side-surface of said base extraction electrode and on the side-surface of said gate electrode a first side-wall layer composed of said second insulator layer, said third insulator layer, and said second conductor layer; (f) performing an etching step, in which said first side-wall layer serves as an etch mask, to remove said third and second insulator layers from said emitter formation region, for self-aligned formation of an opening for an emitter extraction electrode; (g) depositing a third conductor layer on the entirety of said semiconductor substrate, selectively etching said third conductor layer to form above said opening said emitter extraction electrode, and performing an etching process step to remove said second conductor layer of said first side-wall layer from other side-surfaces of said base extraction electrode except the side-surface thereof covered with said emitter extraction electrode, and from the side-surface of said gate electrode, to form a second side-wall layer; (h) forming said source-drain formation region in a manner of self-alignment with said second side-wall layer.