Patent EP0744754A2 successfully refreshed from Google Patents.
EP0744754A2
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Method and apparatus for hot carrier injection
Assignee: AT&T Inc
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Filing: 1996-05-15
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Granted: —
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Expires: 2016-05-15
Abstract
Abstract The invention is directed to a memory cell with a floating gate and a method for charging the floating gate using channel-initiated secondary electron injection (CISEI). In the device of the present invention, a positive bias voltage of about 1.1 volts to about 3.3 volts is applied between the drain and the source when introducing charge onto the floating gate. A negative bias voltage of about -0.5 volts or more negative is applied to the substrate and the source. The drain substrate bias induces a sufficient amount of secondary hot electrons to be formed with a sufficient amount of energy to overcome the energy barrier between the substrate and the floating gate to charge the floating gate.
Inventors
- 👤 Jeffrey Devin Bude
- 👤 Mark Richard Pinto
- 👤 Kevin John O'connor
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 21:48
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
131 words
A semiconductor n-channel device formed on a substrate comprising: a source region and a drain region in the substrate; a dielectric layer deposited on the substrate, a floating gate electrode formed on the dielectric layer wherein at least a portion of the floating gate electrode is overlying the drain region, an additional dielectric material formed on the surface of the floating gate electrode, and a control gate electrode formed on the additional dielectric material; a means for negatively charging the floating gate including a means for applying a negative substrate-source bias voltage (V B - V S ) of about -0.5 volts or more negative and a means for applying a drain-source bias voltage (V D - V S ) of about 1.1 volts to about 3.3 volts to the device.
Claim 2
Dependent Claim
28 words
The semiconductor device of claim 1 wherein the bias between the substrate and the source is about -0.5 volts to about -3 volts when charging the floating gate.
Claim 3
Dependent Claim
22 words
The semiconductor device of claim 1 wherein the bias between the control gate and the source is less than about 10 volts.
Claim 4
Dependent Claim
40 words
The semiconductor device of claim 3 wherein the source voltage is about 0 volts, the drain voltage is about 1.1 to about 3.3 volts, and the substrate voltage is about -0.5 to about -3 volts when charging the floating gate.
Claim 5
Dependent Claim
16 words
The semiconductor device claim 4 wherein the control gate voltage is less than the drain voltage.
Claim 6
Dependent Claim
14 words
The semiconductor device of claim 1 wherein the substrate comprises a region of silicon-germanium.
Claim 7
Dependent Claim
25 words
The semiconductor device of claim 6 wherein the drain is formed in the silicon-germanium region and the source is not formed in the silicon-germanium region.
Claim 8
Dependent Claim
17 words
The semiconductor device of claim 6 wherein the source and drain are formed in the silicon-germanium region.
Claim 9
Dependent Claim
15 words
The semiconductor device of claim 1 wherein the device is a stacked gate n-channel device.
Claim 10
Dependent Claim
157 words
A semiconductor n-channel device comprising: a source region and a drain region in a semiconductor substrate; a dielectric layer deposited on the substrate; a floating gate electrode formed on the dielectric layer wherein a portion of the floating gate electrode overlies the drain region; an additional dielectric material formed on the surface of the floating gate electrode, a control gate electrode formed on the additional dielectric material; and a connection for applying a drain-source bias of about 1.1 volt to about 3.3 volts to the device wherein the device has a drain junction depth of about 0.05µm or less, an n-type dopant concentration in the drain of at least about 5 x 10 19 /cm 3 , a p-type dopant concentration of at least about 2 x 10 18 /cm 3 at the drain substrate junction and wherein the thickness of the dielectric layer between the floating gate and the substrate is about 10 nm or less.
Claim 11
Independent Claim
78 words
A method for charging an n-channel floating gate of a memory cell having a source, drain, control gate, floating gate, and a substrate comprising: applying a voltage to the drain terminal of the cell to effect a positive bias of about 1.1 volts to about 3.3 volts between the drain and the source and; applying a negative voltage to the substrate to effect a negative bias of at least about -0.5 volts between the substrate and the source.
Claim 12
Dependent Claim
23 words
The method of claim 11 wherein the negative bias between the substrate and the source is about -0.5 volts to about -3 volts.
Claim 13
Dependent Claim
55 words
The method of claim 11 wherein the voltage applied to the source is zero, the voltage applied to the substrate is about -0.5 to about -3 volts, the voltage applied to the control gate is less than about 10 volts and the voltage applied to the drain is about 1.1 volts to about 3.3 volts.
Claim 14
Dependent Claim
25 words
The method of claim 13 wherein the voltage applied to the control gate is less than or equal to the voltage applied to the drain.
Claim 15
Dependent Claim
127 words
An array of floating gate memory cells comprising: at least two cells each cell having a source region and a drain region formed in a substrate, a dielectric layer deposited on the substrate, a floating gate electrode formed on the dielectric layer, an additional dielectric material formed on the surface of the floating gate electrode, and a control gate electrode formed on the additional dielectric material, and a connection for applying a negative substrate-source bias voltage of at least about -0.5 volts to the substrate wherein the substrate of at least one cell is electrically connected to a first select and wherein the substrate of at least one cell is connected to a second select, wherein the first and second selects are electrically isolated from each other.
Claim 16
Dependent Claim
57 words
The array of claim 15 wherein the bias between the drain and the source of each cell in the array is about 1.1 volts to about 3.3 volts, and the substrate source bias voltage applied to the substrate in each cell in the array is about -0.5 volts to about -3 volts when charging the floating gate.
Claim 17
Dependent Claim
55 words
The array of claim 16 wherein the source voltage applied to each cell in the array is about 0 volts, the drain voltage applied to each cell in the array is about 1.1 volts to about 3.3 volts, and the substrate voltage is about -0.5 volts to about -3 volts when charging the floating gate.
Claim 18
Dependent Claim
18 words
The array of claim 17 wherein the voltage supplied to the control gate is less than about 10V.
Claim 19
Dependent Claim
21 words
The array of claim 18 wherein the voltage supplied to the control gate is about 1.1 volts to about 3.3 volts.
Claim 20
Dependent Claim
25 words
The array of claim 19 wherein the voltage supplied to the control gate is less than or equal to the voltage applied to the drain.
References Cited (Backward Citations)
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