Patent US4440261A successfully refreshed from Google Patents.
Patent EP0744748A2 successfully refreshed from Google Patents.
EP0744748A2
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EP
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High memory capacity DIMM with data and state memory
Assignee: Graphics Properties Holdings Inc
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Filing: 1996-05-14
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Granted: —
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Expires: 2016-05-14
Abstract
Abstract A high memory capacity dual in-line memory modules (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system includes a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities. <IMAGE>
Inventors
- 👤 James Pierce Laudon
- 👤 Daniel Edward Lenoski
- 👤 John Manton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 11:50
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/04; G06; G06F; G06F12/00
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
43 words
A dual in-line memory module (DIMAQ comprising: a circuit board; first memory means, mounted on said circuit board, for storing data; and second memory means, mounted on said circuit board, for storing directory information corresponding to at least a portion of said data.
Claim 2
Dependent Claim
23 words
The DIMM of claim 1, comprising: further means for permitting said first memory means and said second memory means to be accessed separately.
Claim 3
Dependent Claim
47 words
The DIMM of claim 2, wherein said further means comprises a connector, said connector having a plurality of pads, said pads including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads.
Claim 4
Dependent Claim
70 words
The DIMM of claim 3, wherein said plurality of pads has the following arrangement: said first group of data pads and said first group of address pads are electrically coupled to said first memory means; and said second group of data pads and said second group of address pads are electrically coupled to said second memory means, wherein said arrangement permits independent addressing of said first and second memory means.
Claim 5
Dependent Claim
22 words
The DIMM of claim 4, wherein said plurality of pads further comprises separate control pads for said first and second memory means.
Claim 6
Dependent Claim
67 words
The DIMM of claim 4, wherein said connector is an edge connector having two sides and at least 122 pads per side, said first group of address pads includes at least 12 pads, said second group of address pads includes at least 12 pads, said first group of data pads includes at least 72 pads, and said second group of data pads includes at least 16 pads.
Claim 7
Dependent Claim
29 words
The DIMM of any of the preceding claims, wherein said first memory means and said second memory means each comprise a plurality of dynamic random access memory (DRAM) chips.
Claim 8
Dependent Claim
38 words
The DIMM of any of the preceding claims, further comprising a phase locked loop clock driver coupled to said first and second memory means and a buffer for buffering address and control signals for said first memory means.
Claim 9
Dependent Claim
42 words
The DIMM of any of the preceding claims, wherein said first memory means is logically organized into memory blocks, and said second memory means is configured for storing information about where data stored in a group of said memory blocks is cached.
Claim 10
Dependent Claim
41 words
The DIMM of any of the preceding claims, wherein said first memory means is logically organized into memory blocks, and said second memory means is configured for storing access rights for the data stored in a group of said memory blocks.
Claim 11
Dependent Claim
41 words
The DIMM of any of the preceding claims, wherein said first memory means is logically organized into memory blocks, and said second memory means is configured for storing cache state information about data stored in a group of said memory blocks.
Claim 12
Dependent Claim
27 words
The DIMM of claim 4, wherein said first memory means and said second memory means each comprise a plurality of synchronous dynamic random access memory (SDRAM) chips.
Claim 13
Dependent Claim
30 words
The DIMM of claim 12, wherein said first memory means is divided into a first memory bank portion of SDRAM chips and a second memory bank portion of SDRAM chips.
Claim 14
Dependent Claim
65 words
The DIMM of claim 13, wherein said first memory bank portion and said second memory bank portion each comprises at least nine (9) SDRAM chips, each of said at least nine (9) SDRAM chips being two megabits (2M) deep and eight (8) bits wide, and wherein said second memory means comprises at least one one megabit (1M) deep by sixteen (16) bit wide SDRAM chip.
Claim 15
Dependent Claim
65 words
The DIMM of claim 13, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips, each of said at least eighteen (18) SDRAM chips being four megabits (4M) deep and four (4) bits wide, and wherein said second memory means comprises at least two two megabit (2M) deep by eight (8) bit wide SDRAM chips.
Claim 16
Dependent Claim
26 words
The DIMM of claim 15, wherein said printed circuit board comprises a first circuit board supporting a second circuit board in a parallel, piggy back configuration.
Claim 17
Dependent Claim
77 words
The DIMM of claim 13, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips, each of said at least eighteen (18) SDRAM chips being sixteen megabits (16M) deep and four (4) bits wide; wherein said first group of address pads includes at least 14 pads; and wherein said second memory means comprises at least two eight megabit (8M) deep by eight (8) bit wide SDRAM chips.
Claim 18
Dependent Claim
41 words
A dual in-line memory module (DIMM) comprising: a circuit board; a data memory mounted on said circuit board; a state memory mounted on said circuit board; and means for permitting said data memory and said state memory to be accessed separately.
Claim 19
Dependent Claim
44 words
The DIMM of claim 18, wherein said means comprises a connector having a plurality of pads, said pads including a first group of address pads, a second group of address pads, a first group of data pads, and a second group of data pads.
Claim 20
Dependent Claim
69 words
The DIMM of claim 19, wherein said plurality of pads has the following arrangement: said first group of data pads and said first group of address pads are electrically coupled to said data memory; and said second group of data pads and said second group of address pads are electrically coupled to said state memory, wherein said arrangement permits independent addressing of said data memory and said state memory.
Claim 21
Dependent Claim
23 words
The DIMM of claim 19, wherein said plurality of pads further comprises separate control pads for said data memory and said state memory.
Claim 22
Dependent Claim
67 words
The DIMM of claim 20, wherein said connector is an edge connector having two sides and at least 122 pads per side, said first group of address pads includes at least 12 pads, said second group of address pads includes at least 12 pads, said first group of data pads includes at least 72 pads, and said second group of data pads includes at least 16 pads.
Claim 23
Dependent Claim
28 words
The DIMM of any of claims 18 to 22, wherein said data memory and said state memory each comprise a plurality of dynamic random access memory (DRAM) chips.
Claim 24
Dependent Claim
39 words
The DIMM of any of claims 18 to 23, further comprising a phase locked loop clock driver coupled to said data memory and said state memory, and a buffer for buffering address and control signals for said data memory.
Claim 25
Dependent Claim
41 words
The DIMM of any of claims 18 to 24, wherein said data memory is logically organized into memory blocks, and said state memory is configured for storing information about where data stored in a group of said memory blocks is cached.
Claim 26
Dependent Claim
40 words
The DIMM of any of claims 18 to 25, wherein said data memory is logically organized into memory blocks, and said state memory is configured for storing access rights for the data stored in a group of said memory blocks.
Claim 27
Dependent Claim
40 words
The DIMM of any of claims 18 to 26, wherein said data memory is logically organized into memory blocks, and said state memory is configured for storing cache state information about data stored in a group of said memory blocks.
Claim 28
Dependent Claim
25 words
The DIMM of claim 20, wherein said data memory and said state memory each comprise a plurality of synchronous dynamic random access memory (SDRAM) chips.
Claim 29
Dependent Claim
29 words
The DIMM of claim 28, wherein said data memory is divided into a first memory bank portion of SDRAM chips and a second memory bank portion of SDRAM chips.
Claim 30
Dependent Claim
64 words
The DIMM of claim 29, wherein said first memory bank portion and said second memory bank portion each comprise at least nine (9) SDRAM chips, each of said at least nine (9) SDRAM chips being two megabits (2M) deep and eight (8) bits wide, and wherein said state memory comprises at least one one megabit (1M) deep by sixteen (16) bit wide SDRAM chip.
Claim 31
Dependent Claim
64 words
The DIMM of claim 29, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips, each of said at least eighteen (18) SDRAM chips being four megabits (4M) deep and four (4) bits wide, and wherein said state memory comprises at least two two megabit (2M) deep by eight (8) bit wide SDRAM chips.
Claim 32
Dependent Claim
26 words
The DIMM of claim 31, wherein said printed circuit board comprises a first circuit board supporting a second circuit board in a parallel, piggy back configuration.
Claim 33
Dependent Claim
75 words
The DIMM of claim 29, wherein said first memory bank portion and said second memory bank portion each comprise at least eighteen (18) SDRAM chips, wherein each of said at least eighteen (18) SDRAM chips is sixteen megabits (16M) deep and four (4) bits wide; where said first group of address pads includes 14 pads; and wherein said state memory comprises at least two eight megabit (8M) deep by eight (8) bit wide SDRAM chips.
References Cited (Backward Citations)
No citation records indexed.
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