Patent EP0740343A2 successfully refreshed from Google Patents.
EP0740343A2
Expired / Lapsed
EP
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Structure of chip on chip mounting preventing crosstalk noise
Assignee: Panasonic Holdings Corp
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Filing: 1996-04-17
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Granted: —
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Expires: 2016-04-17
Abstract
Abstract The present invention is intended to solve a problem of crosstalk noise in a so-called system module, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap, and invites malfunctioning of semiconductor devices. As shown in Fig.1, the semiconductor device comprises a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, a second semiconductor chip 5 having a second electrode pad 6 located at a corresponding place and a second wiring layer 10 in the main surface facing to the first semiconductor chip, a bump 4 for electrically coupling first electrode pad 2 and second electrode pad 6 together, an insulation layer 8 disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5 facing to each other, and an electro-conductive layer 7 disposed between the main surfaces of first semiconductor chip and second semiconductor chip facing to each other.
Inventors
- 👤 Takayuki Yoshida
- 👤 Takashi Otsuka
- 👤 Hiroaki Fujimoto
- 👤 Tadaaki Mimura
- 👤 Ichiro Yamane
- 👤 Takio Yamashita
- 👤 Toshio Matsuki
- 👤 Yoahiaki Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 18:26
CPC Classifications
H; H10; H10W; H10W78/00; H10W42/00; H10W42/20; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W90/00; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/071; H10W72/072; H10W72/073; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/851; H10W72/853; H10W72/856; H10W90/20; H10W90/22; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
114 words
A semiconductor device comprising: a first semiconductor chip having a first electrode pad and a first wiring layer disposed in the main surface; a second semiconductor chip having a second electrode pad located at a corresponding place and a second wiring layer disposed in the main surface facing to said first semiconductor chip; a coupling member for electrically coupling said first electrode pad and said second electrode pad together; an insulation member disposed between said main surfaces, facing to each other, of said first semiconductor chip and said second semiconductor chip; and an electro-conductive member disposed between said main surfaces, facing to each other, of said first semiconductor chip and said second semiconductor chip.
Claim 2
Dependent Claim
50 words
The semiconductor device of claim 1, wherein said insulation member is comprised of an insulation layer formed on at least one of said main surfaces of said first semiconductor chip and said second semiconductor chip, and said electro-conductive member is comprised of an electro-conductive layer formed on said insulation layer.
Claim 3
Dependent Claim
45 words
The semiconductor device of claim 1, wherein said insulation member is comprised of an insulation film having said coupling member in the circumference, and said electro-conductive member is comprised of an electro-conductive layer formed at least on one of the surfaces of said insulation film.
Claim 4
Dependent Claim
31 words
The semiconductor device of claim 1, wherein said insulation member is comprised of an insulation resin, and said electro-conductive member is comprised of an electro-conductive foil buried in said insulation resin.
Claim 5
Dependent Claim
26 words
The semiconductor device of either one of claim 1, claim 2, claim 3 or claim 4, wherein said coupling member is comprised of a metal extrusion.
Claim 6
Dependent Claim
42 words
The semiconductor device of either one of claim 1, claim 2, claim 3 or claim 4, wherein said electro-conductive member is coupled with at least one of ground terminals of said first semiconductor chip, said second semiconductor chip or an external circuit.
Claim 7
Dependent Claim
125 words
A semiconductor device manufacturing method comprising: a process for disposing a first semiconductor chip having a first electrode pad and a first wiring layer on the main surface and a second semiconductor chip having a second electrode pad and a second wiring layer on the main surface, with respective main surface facing to each other; a process for disposing an insulation member between said main surfaces, facing to each other, of said first semiconductor chip and said second semiconductor chip; a process for disposing an electro-conductive member between said main surfaces, facing to each other, of said first semiconductor chip and said second semiconductor chip; and a process for electrically coupling said first electrode pad and said second electrode pad together with a coupling member.
Claim 8
Dependent Claim
67 words
The semiconductor device manufacturing method of claim 7, wherein said process for disposing an insulation member is comprised of a process to form an insulation layer on at least one of said wiring layers of either said first semiconductor chip or said second semiconductor chip, and said process for disposing an electro-conductive member is comprised of a process to form an electro-conductive layer on said insulation layer.
Claim 9
Dependent Claim
140 words
The semiconductor device manufacturing method of claim 7, wherein said coupling process is comprised of a process to couple via an extruded electrode formed on both surfaces of an insulation film; said process for disposing an electro-conductive member is comprised of a process to form an electro-conductive layer on at least one of the surfaces of said insulation film in an area excluding at least said extruded electrode; and said process for disposing an insulation member is comprised of a process to apply an insulation resin on said first semiconductor chip, a process to place said insulation film on said insulation resin so that said first electrode pad comes to said extruded electrode and said second electrode pad to said extruded electrode, respectively facing to each other, and a process to further apply an insulation resin on said insulation film.
Claim 10
Dependent Claim
81 words
The semiconductor device manufacturing method of claim 7, wherein said process for disposing an insulation member and said process for disposing electro-conductive member are comprised of a process to apply an insulation resin on an area of said first semiconductor chip, a process to place an electro-conductive film on said insulation resin covering an area excluding said first electrode pad, and a process to bury said electro-conductive foil in said insulation resin by applying an insulation resin on said electro-conductive foil.
Claim 11
Dependent Claim
37 words
The semiconductor device manufacturing method of either one of claim 7 or claim 8, wherein said process for disposing an electro-conductive member is comprised of a process to form said electro-conductive member by means of electroless plating.
Claim 12
Dependent Claim
48 words
The semiconductor device manufacturing method of either one of claim 7, claim 8, claim 9 or claim 10, further comprising a process for connecting said electro-conductive member with at least one of the ground terminals of said first semiconductor chip, said second semiconductor chip or an external circuit.
Claim 13
Dependent Claim
112 words
A semiconductor device comprising a first semiconductor chip having a first electrode pad, a first wiring layer and a first elements region in the main surface, and a second semiconductor chip having a second electrode pad located at a corresponding place, a second wiring layer and a second elements region in the main surface facing to said first semiconductor chip, wherein said second semiconductor chip has a square measure larger than that of said first semicoductor chip, and said second wiring layer and said second elements region are formed on said second semiconductor chip in an area away from an area facing to said first wiring layer and said first elements region.
Claim 14
Dependent Claim
28 words
The semiconductor device of claim 13, wherein a memory with which an information is erasable and rewritable by irradiating ultraviolet rays is formed in said second elements region.
Claim 15
Dependent Claim
56 words
The semiconductor device of claim 13, wherein the number of said second electrode pads is more than said first electrode pad counts, and the area of said second elements region is smaller than the square measure of said second semiconductor chip minus the total of said first wiring layer area and said first elements region area.
Claim 16
Dependent Claim
99 words
A semiconductor device comprising a first semiconductor chip having a first electrode pad, a first wiring layer and a first elements region in the main surface, and a second semiconductor chip having a second electrode pad located at a corresponding place, a second wiring layer and a second elements region in the main surface facing to said first semiconductor chip, wherein said first semiconductor chip and said second semiconductor chip are disposed so as said wiring of first wiring layer and wiring of second wiring layer cross to each other at a certain optional angle without having mutual contact.
Claim 17
Dependent Claim
104 words
A semiconductor device comprising a first semiconductor chip having a first electrode pad, a first wiring layer and a first elements region in the main surface, and a second semiconductor chip having a second electrode pad located at a corresponding place, a second wiring layer and a second elements region in the main surface facing to said first semiconductor chip, wherein difference between driving voltage of said first semiconductor chip and driving voltage of said second semiconductor chip is smaller than threshold voltage that determines the ON or OFF of either semiconductor chip among the two chips the driving voltage of which is lower.
References Cited (Backward Citations)
No citation records indexed.
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