MOSFET circuit and CMOS logic circuit using the same

Claim 2

The MOSFET circuit as claimed in claim 1, characterized in that said first main current electrode is a source electrode, and said second main current electrode is a drain electrode.

Claim 3

The MOSFET circuit as claimed in claim 1, characterized in that a gate electrode of said first MOSFET is connected to the second main current electrode of said second MOSFET.

Claim 4

The MOSFET circuit as claimed in claim 1, characterized in that said second threshold voltage is lower than said first threshold voltage.

Claim 5

The MOSFET circuit as claimed in claim 1, characterized in that said second threshold voltage is equal to said first threshold voltage.

Claim 6

A CMOS logic circuit including a series connection of a load transistor and a driver transistor, one of said driver transistor and said load transistor including a first MOSFET circuit, said first MOSFET circuit comprising: a first MOSFET having a first threshold voltage, and being connected to the other of said driver transistor and said load transistor; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

Claim 7

The CMOS logic circuit as claimed in claim 6, characterized in that the other of said driver transistor and said load transistor is a MOSFET, and said CMOS logic circuit is a CMOS inverter.

Claim 8

The CMOS logic circuit as claimed in claim 6, characterized in that said load transistor comprises M (M is an integer greater than one) MOSFETs connected in series, and said driver transistor comprises M said first MOSFET circuits connected in parallel, and said CMOS logic circuit is a NOR circuit.

Claim 9

The CMOS logic circuit as claimed in claim 6, characterized in that said load transistor comprises M (M is an integer greater than one) MOSFETs connected in parallel, and said driver transistor comprises M said first MOSFET circuits connected in series, and said CMOS logic circuit is a NAND circuit.

Claim 10

The CMOS logic circuit as claimed in claim 6, characterized in that the other of said driver transistor and said load transistor includes a second MOSFET circuit, said second MOSFET comprising: a third MOSFET having a third threshold voltage, and being connected with said first MOSFET circuit in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 11

The CMOS logic circuit as claimed in claim 10, characterized in that said CMOS logic circuit is a CMOS inverter.

Claim 12

The CMOS logic circuit as claimed in claim 10, characterized in that said driver transistor comprises M (M is an integer greater than one) said first MOSFET circuits connected in parallel, and said load transistor comprises M said second MOSFET circuits connected in series, and said CMOS logic circuit is a NOR circuit.

Claim 13

The CMOS logic circuit as claimed in claim 10, characterized in that said driver transistor comprises M (M is an integer greater than one) said first MOSFET circuits connected in series, and said load transistor comprises M said second MOSFET circuits connected in parallel, and said CMOS logic circuit is a NAND circuit.

Claim 14

A buffer circuit including a first CMOS inverter and a second CMOS inverter alternately connected in cascade, wherein a load transistor of said first CMOS inverter comprises: a first MOSFET having a first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 15

A CMOS logic circuit including a low threshold CMOS logic circuit and at least one switching circuit, said low threshold CMOS logic circuit including MOSFETs with a threshold voltage lower than a first threshold voltage, and said switching circuit being connected between a power supply terminal of said low threshold CMOS logic circuit and a power supply, wherein said switching circuit comprises: a first MOSFET having said first threshold voltage, and being connected between said power supply and said power supply terminal of said low threshold CMOS logic circuit; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET.

Claim 16

The CMOS logic circuit as claimed in claim 15, characterized in that said switching circuit is connected between a high potential terminal of said power supply and a high potential power supply terminal of said low threshold CMOS logic circuit.

Claim 17

The CMOS logic circuit as claimed in claim 15, characterized in that said switching circuit is connected between a low potential terminal of said power supply and a low potential power supply terminal of said low threshold CMOS logic circuit.

Claim 18

The CMOS logic circuit as claimed in claim 16, characterized in that said switching circuit is further connected between a low potential terminal of said power supply and a low potential power supply terminal of said low threshold CMOS logic circuit.

Claim 19

The CMOS logic circuit as claimed in claim 15, characterized in that said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a first buffer connected to a non-inverted sleep signal input terminal of said CMOS logic circuit, and a second buffer connected to an inverted sleep signal input terminal of said CMOS logic circuit, wherein said first buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, and a load transistor of said first CMOS inverter comprises: a first MOSFET having said first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET, and wherein said second buffer comprises said second CMOS inverter and said first CMOS inverter alternately connected in cascade.

Claim 20

The CMOS logic circuit as claimed in claim 15, characterized in that said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a buffer connected to a non inverted sleep signal input terminal of said CMOS logic circuit, wherein said buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, and a load transistor of said first CMOS inverter comprises: a first MOSFET having said first threshold voltage, and being connected with a driver transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a driver transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a load transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 21

The CMOS logic circuit as claimed in claim 15, characterized in that said CMOS logic circuit is switched between a sleep mode and an active mode by a sleep signal externally fed, and further comprises a buffer connected to an inverted sleep signal input terminal of said CMOS logic circuit, wherein said buffer comprises a first CMOS inverter and a second CMOS inverter alternately connected in cascade, wherein a driver transistor of said first CMOS inverter comprises: a first MOSFET having said first threshold voltage, and being connected with a load transistor of said first CMOS inverter in series; and a second MOSFET having a second threshold voltage lower than said first threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET, and a second main current electrode connected to a gate electrode of said first MOSFET, and wherein a load transistor of said second CMOS inverter comprises: a third MOSFET having a third threshold voltage, and being connected with a driver transistor of said second CMOS inverter in series; and a fourth MOSFET having a fourth threshold voltage lower than said third threshold voltage, and having a gate electrode and a first main current electrode connected to a backgate electrode of said third MOSFET, and a second main current electrode connected to a gate electrode of said third MOSFET.

Claim 22

A CMOS logic circuit comprising: an internal CMOS logic circuit including a set of M (M is an integer equal to or greater than one) driver transistors and a set of M load transistors, said internal CMOS logic circuit changing its operation mode in response to an external control signal; and a first MOSFET connected to a first MOSFET circuit constituting one of said set of driver transistors and said set of load transistors, wherein said first MOSFET has a same channel type as said first MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said first MOSFET circuit, and a second main current electrode connected to said external control signal.

Claim 23

The CMOS logic circuit as claimed in claim 22, further characterized by comprising a second MOSFET connected to a second MOSFET circuit constituting the other of said set of driver transistors and said set of load transistors, wherein said second MOSFET has a same channel type as said second MOSFET circuit, and comprises a gate electrode and a first main current electrode connected to a backgate electrode of said second MOSFET circuit, and a second main current electrode connected to an inverted signal of said external control signal.

Claim 24

The CMOS logic circuit as claimed in claim 23, characterized in that a threshold voltage of each of said first MOSFET and said second MOSFET is lower than a threshold voltage of MOSFETs included in said internal CMOS logic circuit.

Claim 25

The CMOS logic circuit as claimed in claim 22, characterized in that said internal CMOS logic circuit comprises one or more CMOS inverters.

Claim 26

The CMOS logic circuit as claimed in claim 22, characterized in that said internal CMOS logic circuit comprises a transmission gate.

Claim 27

The CMOS logic circuit as claimed in claim 22, characterized in that said internal CMOS logic circuit comprises a memory cell, and said control signal is a word line signal.

Claim 28

The CMOS logic circuit as claimed in claim 22, characterized in that said control signal is a sleep signal which switches a mode of said internal CMOS logic circuit into a sleep mode or into an active mode.

Claim 29

The CMOS logic circuit as claimed in any one of claims 1 - 28, characterized in that each MOSFET of said CMOS logic circuit is a SOIFET which is formed on a SOI (Semiconductor On Insulator) substrate.

Claim 30

The CMOS logic circuit as claimed in claim 29, characterized in that carrier concentration of a body of each said low threshold MOSFET is controlled such that said body becomes a fully depleted state.

Claim 31

The CMOS logic circuit as claimed in claim 29, characterized in that carrier concentration of a body of each said low threshold MOSFET is controlled such that said body becomes a partially depleted state.