Abstract A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/ o C. In a preferred embodiment, the dielectric material is a fluoropolymer with a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.
An integrated circuit testing board (10) comprising: a plurality of conductive testing layers (14); a dielectric material (12) surrounding and electrically isolating said plurality of conductive testing layers from one another, wherein said dielectric material has a first coefficient of thermal expansion; and a constraint layer (18,20) disposed in said dielectric material wherein said constraint layer has a second coefficient of thermal expansion substantially less than said first coefficient of thermal expansion.
Claim 2
Dependent Claim
34 words
The testing board of claim 1 wherein said constraint layer is an iron-nickel alloy comprising about 30-40 percent nickel by weight, about 0.4 percent manganese by weight, and about 0.1 percent carbon by weight.
Claim 3
Dependent Claim
33 words
The testing board of claim 1 wherein a surface of said testing board comprises contacts for touching an integrated circuit on a semiconductor wafer and said surface is thermally coexpansive with said wafer.
Claim 4
Dependent Claim
13 words
The testing board of claim 3 wherein said wafer is a silicon wafer.
Claim 5
Dependent Claim
19 words
The testing board of claim 1 wherein said board has a coefficient of thermal expansion substantially similar to silicon.
Claim 6
Dependent Claim
22 words
The testing board of claim 1 wherein said dielectric material is thermally stable at a temperature greater than about 150 o C.
Claim 7
Dependent Claim
13 words
The testing board of claim 1 wherein said dielectric material comprises a fluoropolymer.
Claim 8
Dependent Claim
79 words
A board (10) for testing an integrated circuit, comprising: a plurality of substantially parallel conductive testing layers (14); a dielectric material (12) disposed around and electrically isolating said testing layers from one another, wherein said dielectric material comprises a fluoropolymer and is substantially stable at a temperature greater than about 150 o C; and a constraint layer (18,20) disposed in said dielectric material wherein said constraint layer has a coefficient of thermal expansion of about 1-6 ppm/ o C.
Claim 9
Dependent Claim
23 words
The board of claim 8 wherein said constraint layer is an iron-nickel alloy having a nickel composition of about 30-40 percent by weight.
Claim 10
Dependent Claim
31 words
The board of claim 9 wherein said dielectric material further includes a filler comprising about 80 percent by weight of said dielectric material, wherein said filler is a silica or ceramic.
References Cited (Backward Citations)
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