Integrated circuit testing board having constrained thermal expansion characteristics

Abstract

Abstract A board (10) for testing an integrated circuit disposed on a semiconductor wafer. The board contains a plurality of substantially parallel signal layers (14) and power planes (16) that are supported and electrically isolated by a dielectric material (12). One or more constraint layers (18,20) are disposed in the dielectric material, and the constraint layers have a coefficient of thermal expansion of about 1-6 ppm/ o C. In a preferred embodiment, the dielectric material is a fluoropolymer with a ceramic or silica filler, and the constraint layers are an iron-nickel alloy of about 30-40 percent nickel by weight. The board has thermal expansion characteristics substantially similar to silicon to ensure good contact to a silicon wafer during burn-in testing.

Inventors

• 👤 Barbara Vasquez
• 👤 John W. Stafford
• 👤 William M. Williams

Bibliographic Details