Patent EP0730224A2 successfully refreshed from Google Patents.
EP0730224A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and apparatus for instruction issue
Assignee: Fujitsu Ltd
•
Filing: 1996-03-01
•
Granted: —
•
Expires: 2016-03-01
Abstract
Abstract An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions. <IMAGE>
Inventors
- 👤 Michael C. Shebanow
- 👤 John Gmuender
- 👤 Michael A. Simone
- 👤 John R.F.S Szeto
- 👤 Takumi Maruyama
- 👤 Deforest W. Tovey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 08:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3854; G06F9/3856; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
149 words
A method for selecting two oldest instructions from a plurality of instructions waiting to be executed, each of the plurality of instructions indicating at least one register, the method comprising the steps of: setting bits of an eligible instructions vector, each bit being indicative of a corresponding one of the plurality of instructions waiting to be executed that have said indicated registers available for such execution; selecting a first oldest instruction from said ones of the plurality of instructions waiting to be executed corresponding to said set bits of the eligible instructions vector; resetting the bit of the eligible instructions vector corresponding to the first oldest instruction; selecting a second oldest instruction from said ones of the plurality of instructions waiting to be executed corresponding to said set bits of the eligible instructions vector; and resetting the bit of the eligible instructions vector corresponding to the second oldest instruction.
Claim 2
Independent Claim
265 words
A method for selecting the two oldest instructions from a plurality of instructions waiting to be executed, each of the plurality of instructions indicating at least one register, the method comprising the steps of: receiving a plurality of instructions; setting bits of a first eligible instructions vector, each bit of the first eligible instructions vector being indicative of a corresponding one of the received plurality of instructions that have said indicated registers available for such execution; setting bits of a second eligible instructions vector, each bit being indicative of a corresponding one of the plurality of instructions waiting to be executed that have said indicated registers available for such execution; if one of said bits of the second eligible instructions vector is set, selecting a first oldest instruction from said ones of the plurality of instructions waiting to be executed corresponding to said set bits of the second eligible instructions vector; if one of said bits of the second eligible instructions vector is not set, selecting a first oldest instruction from said received instructions; resetting the bit of the eligible instructions vector corresponding to the first oldest instruction; if one of said bits of the second eligible instructions vector is set, selecting a second oldest instruction from said ones of the plurality of instructions waiting to be executed corresponding to said set bits of the eligible instructions vector; if one of said bits of the second eligible instructions is not set, selecting a second oldest instruction from said received instructions; and resetting the bit of the eligible instructions vector corresponding to the second oldest instruction.
Claim 3
Dependent Claim
161 words
An instruction selector for selecting two oldest instructions from N instructions, each of the N instructions indicating registers for executing such instruction, the instruction selector comprising: a dependency checker for detecting the availability of the registers for executing the N instructions and for providing a signal indicative of ones of the N instructions that may be executed responsive either to such availability or to a selected instruction signal indicative of the two oldest instructions; an instruction queue coupled to the dependency checker for providing a signal indicative of age of each of the N instructions, for storing the N instructions, and for providing the selected two oldest instructions responsive to a signal indicative of the two oldest instructions; and an oldest-instruction selector coupled to the dependency checker and to the instruction queue for generating the selected instruction signal responsive to the signal indicative of the ones of the N instructions that may be executed and to the signal indicative of age.
Claim 4
Dependent Claim
175 words
The instruction selector of claim 3 wherein the oldest-instruction selector comprises: a first oldest instruction selector for determining the oldest instruction of said ones of the N instructions that may be executed responsive both to the signal indicative of the ones of the N instructions that may be executed and to the signal indicative of age, for generating a first oldest-instruction signal responsive to the determined oldest instruction, and for modifying the signal indicative of the ones of the N instructions that may be executed to delete said determined oldest instruction from said ones of the N instructions that may be executed; and a second oldest instruction selector for determining the oldest instruction of the ones of the N instructions that may be executed responsive both to the modified signal indicative of the ones of the N instructions that may be executed and to the signal indicative of age, for generating a second oldest-instruction signal responsive to such determined oldest instruction, wherein the selected instruction signal is indicative of the first and second oldest-instruction signals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.