Semiconductor memory device

Claim 2

An array according to claim 1, wherein said thin film has a thickness (t 1 ) in the range 1 to 30nm.

Claim 3

An array according to claim 2, wherein said thin film has a thickness in the range 3 to 20nm.

Claim 4

An array according to claim 3, wherein said thin film has a thickness in the range 5 to 15nm.

Claim 5

An array according to any preceding claim, wherein said thin film is of silicon oxide, silicon nitride or silicon oxynitride.

Claim 6

An array according to any preceding claim, wherein said thin film is of an insulator material containing tantalum (Ta).

Claim 7

An array according to claim 6, wherein said thin film is of tantalum oxide.

Claim 8

An array according to any preceding claim, wherein said floating gate is of polysilicon.

Claim 9

An array according to claim 8, wherein metal is contained in said polysilicon.

Claim 10

An array according to claim 9, wherein said metal is a refractory metal.

Claim 11

An array according to any of claims 1 to 7, wherein said floating gate is of refractory metal.

Claim 12

An array according to either of claims 10 or 11 wherein said refractory metal is at least one of the metals tungsten, titanium, tantalum or molybdenum

Claim 13

An array according to any of claims 1 to 7, wherein said floating gate is of silicide or polyside material.

Claim 14

An array according to any preceding claim, wherein said thin film is the oxidation or nitridation product of a process in which (a) one or both said edge surfaces, or (b) said side wall surface, of said floating gate are treated by oxidation or nitridation.

Claim 15

An array according to any preceding claim wherein said substrate (1011) comprises a silicon semiconductor layer (1014) on an insulator layer (1012), said memory cell having said source, drain, and channel provided in a respective portion (1013) of said semiconductor layer.

Claim 16

An array according to any preceding claim wherein in each memory cell the capacitance between said floating gate and the substrate is greater than the capacitance between said floating gate and said control gate.

Claim 17

An array according to any preceding claim wherein in each memory cell said floating gate is insulated from said channel by an insulation layer (1006) of silicon oxynitride.

Claim 18

An array according to any preceding claim wherein said plurality of memory cells are arranged in a matrix of rows and columns, the memory cells (11, 21, 31; 14, 24, 34) in each column being arranged in series with their respective source (5) electrically connected to the drain (6) of the preceding memory cell (21, 31, 41; 24, 34, 44).

Claim 19

An array according to any preceding claim wherein said substrate (1007) is a bulk semiconductor substrate, said plurality of memory cells are arranged in a matrix of rows and columns, the drain (6), source (5) and channel of each memory cell (11, 21, 31, 41; 14, 24, 34, 44) in respective columns are defined in a respective common well (1003) electrically insulated from the common wells of adjacent columns; and respective conductive lines (4) are connected to the control gate (1) of each memory cell in respective rows (11, 21, 31, 41; 14, 24, 34, 44).

Claim 20

An array according to any preceding claims 1 to 18, wherein said substrate (1011) is a semiconductor-on-insulator substrate, said plurality of memory cells are arranged in a matrix of rows and columns, the drain (6), source (5), and channel of each memory cell (11, 21, 31, 41; 14, 24, 34, 44) in respective columns are defined in respective separated islands (1013) of the semiconductor layer (1014) of said semiconductor-on-insulator substrate, and respective conductive lines (4) are connected to the control gate (1) of each memory cell (11, 21, 31, 41; 14, 24, 34, 44) in respective rows.

Claim 21

A programmed read-only memory array consisting of a memory array according to any preceding claim, wherein said antifuse region (1004, 1016) of selected memory cells, amongst said plurality of memory cells, are each in a fused low-resistance state, a respective conductive path thus being provided between the respective floating gate and respective control gate of each respective selected memory cell.

Claim 22

A programmable read-only memory device comprising: an OT-PROM memory array according to any preceding claim 1 to 20; means (8, 9, 25) of addressing and writing data to selected memory cells amongst said plurality of memory cells; and means (7, 9, 15, 16, 25) of addressing and reading data from each memory cell amongst said plurality of memory cells.

Claim 23

A device according to claim 22, wherein the memory cells of said OT-PROM memory array are arranged in a matrix of columns and rows, said device further including: a random access memory (155), means (TR3, TR4) of writing data to said random access memory, the data which is to be written therein being the same data which is to be written to memory cells in a column of said OT-PROM memory array; means (TR1, TR2) of reading data from said random access memory; means (153) of collating data read from said random access memory with data read from said memory cells in said column of said OT-PROM memory array for outputting a collation result to indicate whether or not the collated data is the same or is different; means (7, 9, 154) of writing said collation result in at least one other memory cell in said column of memory cells; and means (7, 9, 154) of rewriting said data in memory cells of a next column of said OT-PROM memory array if said collation result indicates that the collated data is different.

Claim 24

A device according to claim 23, wherein said random access memory is a CMOS SRAM.

Claim 26

A device according to claim 25, wherein said input means comprises a photodetector.

Claim 28

A device according to claim 27, wherein said output means comprises a semiconductor laser.

Claim 29

A programmed memory device comprising: a programmed memory array according to claim 21; and means of addressing and reading data from each memory cell amongst said plurality of memory cells.

Claim 30

A method of recording information comprising steps of: providing the one-time programmable read-only memory of claim 1; and in accordance with the information that is to be recorded, applying a first voltage V 1 to the control gate (1001) of selected memory cells to change, in each respective selected memory cell, the resistance value of the respective anti-fuse region (1004;1016) from that of the high resistance thin film, to a lower value, affording electrical connection between the respective control gate (1001) and the respective floating gate (1002) of the respective selected memory cell.

Claim 31

A method according to claim 30 wherein, for the recording of information in a selected memory cell, the channel (1003) thereof is held at a supply voltage or at ground potential (GND) while the channels (1003) of non-selected memory cells are left at a floating voltage.

Claim 32

A method according to claim 31 wherein information recording is performed under the following conditions: { C FG /(C FG +C CG )} ° V 1 ≥ V BD , { C CG /(C FG +C CG )} ° V 2 < V th , V 2 > V th ; where V BD is the voltage between the respective floating gate (1002) and the respective control gate (1001) of the respective selected memory cell when the resistance value of the respective anti-fuse region is changed from its high resistance thin film value to said lower resistance value, V th is the threshold voltage of the respective memory cell, C FG is the capacitance defined between the respective floating gate (1002) and the substrate (1007;1011), C CG is the capacitance defined between the respective floating gate and the respective control gate (1001), V 1 is the voltage applied to the respective control gate (1001) for recording, and V 2 is a voltage set for reading the selected memory cell, which voltage V 2 is to be applied to the respective control gate (1001).