Patent EP0726664A2 successfully refreshed from Google Patents.
EP0726664A2
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EP
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Multiport analyzing time stamp synchronizing and parallel communicating
Assignee: Wandel and Goltermann Techologies Inc
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Filing: 1995-10-12
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Granted: —
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Expires: 2015-10-12
Abstract
Abstract A plurality of digital transmission network analyzers (36) are arranged to analyze and compare the appearance of a data packet on the plurality of ports of a network (12). Each analyzer (36) has its own internal clock (50) for time stamping of data packets in addition to other internal timing purposes. In order to synchronize the time stamping of the packet as it appears to each analyzer at each different port, the clock outputs of the several analyzers are connected together; and a controlling CPU (40) commands one of the analyzers to supply the master clock to the others. That master analyzer then commands the other analyzers to disable or disconnect their own clocks, thereby all of the analyzers involved in a given test are under timing control of the clock of the master analyzer. Packet headers and time stamps are transmitted between analyzers for comparison, analysis and reporting to the controlling CPU. This analyzer intercommunication is effected over a separate bus (42) that interconnects all of the analyzers and the controlling CPU.
Inventors
- 👤 Jing Zhang
- 👤 Kenneth R. Gramley
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:18
CPC Classifications
H; H04; H04L; H04L43/00; H04L7/00; H04L7/0008; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0638; H04J3/0658
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
152 words
An analyzer for use with digital transmission networks with multiple ports, said analyzer having data packet analyzing capability and a facility for participating in the analysis, with synchronization, at multiple ports of a digital transmission network, the analyzer including: a counter, the output of which is used to time stamp data packets received by the analyzer, the input of the counter being interconnectible with the input of the clock of another analyzer; a clock, the output of which is interconnectible with the input of the counter and the counter of another analyzer; and a clock control circuit for selectively interconnecting the clock to the counter and to the counter of another analyzer, and for disabling the connection between the clock and the counter in response to a received clock-disable signal, thereby allowing the clock output of said other analyzer to substitute for the output of the clock having its counter connection disabled.
Claim 2
Dependent Claim
50 words
An analyzer according to claim 1 and further comprising at least one receive-transmit circuit for intercommunicating, separately from said digital transmission network, in either direction with said other analyzer; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command.
Claim 3
Dependent Claim
72 words
An analyzer for digital transmission networks with multiple ports, said analyzer having data packet analyzing capability and a facility for participating in the analysis, with intercommunication with other analyzers, at multiple ports of a digital transmission network, the analyzer including: at least one receive-transmit circuit for intercommunicating, with said other analyzer; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command.
Claim 4
Dependent Claim
41 words
An analyzer according to claim 2 or 3 wherein said receive-transmit circuit is a half-duplex circuit and said receive-transmit control circuit determines, in response to said command, whether the receive-transmit circuit is in the receive mode or in the transit mode.
Claim 5
Dependent Claim
32 words
An analyzer according to claim 2, 3 or 4 wherein said receive-transmit circuit is separate from said digital transmission network and is capable of communicating in either direction with said other analyzer.
Claim 6
Dependent Claim
85 words
An analyzer according to claim 2, 3, 4 or 5 and further comprising a second receive-transmit circuit for intercommunicating, separately from said digital transmission network, in either direction with another analyzer; and a second receive-transmit control circuit for controlling the transmission and reception capability of the second receive-transmit circuit in response to a command, whereby simultaneous receiving and transmitting intercommunication is possible between the analyzer and said other analyzer or in one direction with said other analyzer and in the opposite direction with another analyzer.
Claim 7
Dependent Claim
38 words
An analyzer according to claim 1 or 2 or claim 4, 5 or 6 when appended to claim 2 and further comprising a control computer for causing the issuance of clock-disable commands to operate the clock control circuit.
Claim 8
Dependent Claim
32 words
An analyzer according to claim 2 and further comprising an analysis-control computer for sending control signals to operate the clock control circuit and for sending commands to operate the receive-transmit control circuit.
Claim 9
Dependent Claim
52 words
An analyzer according to claim 1 or 2 or any one of claims 4 to 8 when appended to claim 2 wherein said clock control circuit is also capable of sending to said other network analyzer a clock-disable command, whereby the clock output substitutes for the clock output of said other analyzer.
Claim 10
Dependent Claim
33 words
An analyzer according to claim 9 wherein there are a plurality of other analyzers and each other analyzer that receives a clock-disable command sends a clock-disable command to another of the other analyzers.
Claim 11
Dependent Claim
32 words
An analyzer according to claim 1 or 2 or any one of claims 4 to 8 when appended to claim 2 wherein said received clock-disable signal is received from said other analyzer.
Claim 12
Dependent Claim
149 words
A digital transmission network analyzer system for analyzing networks with multiple ports and data packet analyzing capability and a facility for analyzing, with synchronization and intercommunication, the analyzer system comprising: a plurality of individual network analyzers, each having a counter, responsive to received clock signals for indicating by its count the time elapsed since the counter was last reset, the output of the counter used to time stamp data packets received by the analyzer, each analyzer connected to a different port on the network; a control computer, separate from the analyzers but linked to each analyzer, said computer being programmed to cause the counter of all analyzers to be reset simultaneously prior to the start of a test; and a source of clock signals independent of the control computer and independent of at least one of the analyzers for advancing in synchronism the counters of all of the analyzers.
Claim 13
Dependent Claim
218 words
A digital transmission network analyzer system for analyzing networks with multiple ports, the analyzers of said system having data packet analyzing capability, a facility for analyzing, with synchronization and intercommunication, a digital transmission network with multiple ports, the analyzer system comprising: a plurality of individual network analyzers, each having a local oscillator clock, each analyzer connected to a different port on the network, an analysis-control CPU for controlling the individual analyzers and programming the individual analyzers to perform an analysis; the output of the clock in each of the analyzers being interconnectible with the output of the clock in each of the other analyzers; a clock circuit in each analyzer for: sending to the other network analyzers a clock-disable signal in response to a command by the CPU to provide the clock for all of the analyzers, whereby the clock output is substituted for the clock output of each of the other analyzers, disabling its own clock in response to a clock-disable signal, thereby allowing the clock output of another analyzer to substitute for the output of the disabled clock; at least one receive-transmit circuit for intercommunicating in either direction with the other analyzers; and a receive-transmit control circuit for controlling the transmission and reception capability of the receive-transmit circuit in response to a command from the CPU.
Claim 14
Dependent Claim
20 words
A digital transmission network analyzer system according to claim 13 wherein the clock-disable signal is received from the other analyzer.
Claim 15
Dependent Claim
33 words
A digital transmission network analyzer system according to claim 12, 13, or 14 wherein said source of clock signals is a bit-rate clock source for clocking the transmission of bits throughout the network.
Claim 16
Dependent Claim
31 words
A digital transmission network analyzer system according to claim 12, 13 or 14 wherein said source of clock signals is independent of all of the analyzers and of the control computer.
Claim 17
Dependent Claim
25 words
A digital transmission network analyzer system according to claim 15 wherein said bit-rate clock source is derived from the bit stream flowing in the network.
Claim 18
Dependent Claim
22 words
A digital transmission network analyzer system according to claim 15 wherein said bit-rate clock source is derived from a network master clock.
Claim 19
Dependent Claim
29 words
A digital transmission network analyzer system according to claim 12, 13 or 14 wherein said source of clock signals is independent of the bit stream flowing in the network.
References Cited (Backward Citations)
US4792753A
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