Patent EP0723294A2 successfully refreshed from Google Patents.
EP0723294A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device having a bond pad and a process for forming the device
Assignee: Motorola Solutions Inc
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Filing: 1996-01-19
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Granted: —
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Expires: 2016-01-19
Abstract
Abstract Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.
Inventors
- 👤 Ting-Chen Hsu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 14:21
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W72/00; H10W72/071; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10W70/00; H10W70/60; H10W72/075; H10W72/07551; H10W72/07553; H10W72/50; H10W72/531; H10W72/5363; H10W72/551; H10W72/552; H10W72/5524; H10W72/59; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952; H10W72/981; H10W72/983; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
119 words
A semiconductor device (300) characterised by: a substrate (30); an interconnect (395); a bond pad (394) having a conductive section (398), wherein the bond pad (394) overlies the substrate (30); and a passivation layer (52) including a bond pad opening (62), wherein: the bond pad opening (62) overlies the bond pad (394); the passivation layer (52) overlies a first portion (64) and a second portion (66) of the conductive section (398); the second portion (66) of the conductive section (398) lies adjacent to the interconnect (395); the first portion (64) of the conductive section (398) lies further from the interconnect (395) compared to the second portion (66); and the first portion (64) is wider than the second portion (66).
Claim 2
Dependent Claim
302 words
A semiconductor device (300) characterised by: a substrate (30); a first interconnect (104) and a second interconnect (104); a first bond pad (106) having a first conductive section (398) and a second bond pad (106) having a second conductive section (398), wherein: the first and second bond pads (106) overlie the substrate (30); the first bond pad (106) lies adjacent to the first interconnect (104); and the second bond pad (106) lies adjacent to the second interconnect (104); and a passivation layer (52) including a first bond pad opening (62) and a second bond pad opening (62), wherein: the first bond pad opening (62) overlies the first bond pad (106); the second bond pad opening (62) overlies the second bond pad (106); the passivation layer (52) overlies first and second portions (64 and 66) of the first and second conductive sections (398); the second portion (66) of the first conductive section (398) lies adjacent to the first interconnect (104); the first portion (64) of the first conductive section (398) lies further from the first interconnect (104) compared to the second portion (66) of the first conductive section (398); the second portion (66) of the second conductive section (398) lies adjacent to the second interconnect (104); the first portion (64) of the second conductive section (398) lies further from the second interconnect (104) compared to the second portion (66) of the second conductive section (398); the first bond pad (62) lies closer to a first side of the semiconductor device (300) compared to the second bond pad (62); the second bond pad (62) lies closer to a second side of the semiconductor device (300) that is opposite the first side compared to the first bond pad (62); and each of the first portions (64) is wider than each of the second portions (66).
Claim 3
Dependent Claim
327 words
A semiconductor device (300) characterised by: a first scribe line (40) and a second scribe line (40) that are on opposite sides of the semiconductor device (300); a substrate (30); a first bond pad (106) having a first conductive section (398) and a second bond pad (106) having a second conductive section (398), wherein: the first and second bond pads (106) overlie the substrate (30); the first bond pad (106) lies closer to the first scribe line (40) compared to the second bond pad (106); and the second bond pad (106)lies closer to the second scribe line (40) compared to the first bond pad (106); and a passivation layer (52) including a first bond pad opening (62) and a second bond pad opening (62), wherein: the first bond pad opening (62) overlies the first bond pad (106); the second bond pad opening (62) overlies the second bond pad (106); the passivation layer (52) overlies first portions (64), second portions (66), third portions (68), and fourth portions (69) of the first and second conductive sections (398); for the first conductive section(398): the first and second portions (64 and 66) lie adjacent to opposite sides of the first bond pad opening (62); and the third and fourth portions (68 and 69) lie adjacent to opposite sides of the first bond pad opening (62) and adjacent to the first and second portions (64 and 66); for the second conductive section (398): the first and second portions (64 and 66) lie adjacent to opposite sides of the first bond pad opening (62); and the third and fourth portions (68 and 69) lie adjacent to opposite sides of the second bond pad opening (62) and adjacent to the first and second portions (64 and 66); and the first portions (64) are widest, the second portions are narrowest (66), and the third and fourth portions (68 and 69) have widths that are between widths of the first and second portions (64 and 66).
Claim 4
Dependent Claim
38 words
The semiconductor device of claim 1, 2, or 3, further characterised such that any and all bond pads (106, 394) have a layer (391) that includes a refractory metal, a refractory metal silicide, or a refractory metal nitride.
Claim 5
Dependent Claim
30 words
The semiconductor device of claim 1, 2, or 3, further characterised such that the first portion (64) is in a range of 2-20 times wider than the second portion (66).
Claim 6
Dependent Claim
141 words
A process for forming a semiconductor device (300) characterised by the steps of: forming a bond pad (394) and an interconnect (395) over a semiconductor substrate (30), wherein the bond pad (394) has a conductive section (398); forming a passivation layer (52) over the bond pad (394) and the interconnect (395); and forming a bond pad opening (62) through the passivation layer (52), wherein: the bond pad opening (62) overlies the bond pad (394); the passivation layer (52) overlies a first portion (64) and a second portion (66) of the conductive section (398); the second portion (66) of the conductive section (398) lies adjacent to the interconnect (395); the first portion (64) of the conductive section (398) lies further from the interconnect (395) compared to the second portion (66); and the first portion (64) is wider than the second portion (66).
Claim 7
Dependent Claim
315 words
A process for forming a semiconductor device (300) characterised by the steps of: forming a first bond pad (106), a first interconnect (104), a second bond pad (106), and a second interconnect (104) over a substrate (30), wherein: the first bond pad (106) includes a first conductive section (398) that lies adjacent to the first interconnect (104); and the second bond pad (106) includes a second conductive section (398) that lies adjacent to the second interconnect (104); forming a passivation layer (52) over the first and second bond pads (106); and forming a first bond pad opening (62) and a second bond pad opening (62) through the passivation layer (52), wherein: the first bond pad opening (62) overlies the first bond pad (106); the second bond pad opening (62) overlies the second bond pad (106); the passivation layer (52) overlies first and second portions (64 and 66) of the first and second conductive sections (398); the second portion (66) of the first conductive section (398) lies adjacent to the first interconnect (104); the first portion (64) of the first conductive section (398) lies further from the first interconnect (104) compared to the second portion (66) of the first conductive section (398); the second portion (66) of the second conductive section (398) lies adjacent to the second interconnect (104); the first portion (64) of the second conductive section (398) lies further from the second interconnect (104) compared to the second portion (66) of the second conductive section (398); the first bond pad (106) lies closer to a first side of the semiconductor device (300) compared to the second bond pad (106); the second bond pad (106) lies closer to a second side of the semiconductor device (300) that is opposite the first side compared to the first bond pad (106); and each of the first portions (64) is wider than each of the second portions (66).
Claim 8
Dependent Claim
314 words
A process for forming a semiconductor device (300) characterised by the steps of: forming a first bond pad (106) and a second bond pad (106) over a substrate (30), wherein: the first bond pad (106) includes a first conductive section (398) and lies closer to a first scribe line (40) compared to the second bond pad(106); and the second bond pad (106) includes a second conductive section (398) and lies closer to a second scribe line (40); forming a passivation layer (52) over the first and second bond pads (106); and forming a first bond pad opening (62) and a second bond pad opening (62) through the passivation layer (52), wherein: the first bond pad opening (62) overlies the first bond pad (106); the second bond pad opening (62) overlies the second bond pad (106); the passivation layer (52) overlies first portions (64), second portions (66), third portions (68), and fourth portions (69) of the first and second conductive sections (398); for the first conductive section (398): the first and second portions (64 and 66) lie adjacent to opposite sides of the first bond pad opening (62); and the third and fourth portions (68 and 69) lie adjacent to opposite sides of the first bond pad opening (106) and adjacent to the first and second portions (64 and 66); for the second conductive section (398): the first and second portions (64 and 66) lie adjacent to opposite sides of the first bond pad opening (62); and the third and fourth portions (68 and 69) lie adjacent to opposite sides of the second bond pad opening (62) and adjacent to the first and second portions (64 and 66); and the first portions (64) are widest, the second portions (66) are narrowest, and the third and fourth portions (68 and 69) have widths that are between widths of the first and second portions (68 and 69).
Claim 9
Dependent Claim
36 words
The process of claim 6, 7 or 8, further characterised such that any and all bond pads (106) have a layer (391) that includes a refractory metal, a refractory metal silicide, or a refractory metal nitride.
Claim 10
Dependent Claim
26 words
The process of claim 10, further characterised such that the first portion (64) is in a range of 2-20 times wider than the second portion (66).
References Cited (Backward Citations)
No citation records indexed.
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