EP0720112A1
Expired / Lapsed
EP
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Low consumption analog multiplier
Assignee: STMicroelectronics SRL
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Filing: 1994-12-27
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Granted: —
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Expires: 2014-12-27
Abstract
Abstract The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.
Inventors
- 👤 Melchiorre Bruccoleri
- 👤 Gaetano Cosentino
- 👤 Marco Demicheli
- 👤 Salvatore Portaluri
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 18:31
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/16; G06G7/163
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
119 words
An analog multiplier comprising at least a differential stage composed of a pair of emitter-coupled bipolar transistors (Q3, Q4), to the common emitter node of which a first input current signal (I2) is fed, each transistor of said pair having a base connected to the output node of a respective predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, a second input current signal (I1) and a difference signal (IM-I1) between a preset maximum input current value (IM) and said second input current signal (I1) being respectively forced through said predistortion stages (Q1, Q2), characterized by comprising means capable of generating compensation currents of the base currents of the transistors (Q3, Q4) of said pair.
Claim 2
Dependent Claim
260 words
An analog multiplier according to claim 1, characterized by by the fact that said means comprise a first generator circuit of a first compensation current composed of a fifth transistor (Q5) substantially identical to the bipolar transistors of said pair, through which a current equal to the difference (IM-I2) between said maximum input current value (IM) and said first input current signal (I2) is forced and the base current of which is mirrored on the output node of the predistortion stage (Q1) through which said second input current signal (I1) is forced; a second generator circuit of a second compensation current composed of sixth transistor (Q6) substantially identical to the bipolar transistors of said pair, through which a current identical to said first input current signal (I2) is forced and the base current of which is mirrored on the output node of the predistortion stage (Q2) through which said current difference signal (IM-I2) is forced; a first correction stage composed of a seventh transistor (Q7), substantially identical to said bipolar transistors, through which a second difference current signal (IM-I2) between said maximum input current value (IM) and said first input current signal (I2) is forced and having a base connected to the collector of a first transistor (Q3) of said pair; a second correction stage composed of a eigth transistor (Q8) substantially identical to the bipolar transistors of said pair, through which a current equal to said first input current signal (I2) is forced and having a base connected to the collector of a second transistor (Q4) of said pair.
Claim 3
Dependent Claim
159 words
An analog multiplier according to claim 1, characterized by by the fact that said means comprise a first generator circuit of a first compensation current composed of a fifth transistor (Q5) substantially identical to the bipolar transistors of said pair, through which a current equal to the difference (IM-I2) between said maximum input current value (IM) and said first input current signal (I2) is forced and the base current of which is mirrored on the output node of a first predistortion stage (Q1) through which said second input current signal (I1) is forced; a second generator circuit of a second compensation current composed of a sixth transistor (Q6) substantially identical to the bipolar transistors of said pair, through which a current identical to said first input current signal (I2) is forced and the base current of which is mirrored on the output node of a second predistortion stage (Q2) through which said second input current signal (I1) is forced.
Claim 4
Dependent Claim
67 words
Analog multiplier according to claim 1, wherein said means comprise a current mirror circuit capable of forcing a current (IM/β) proportional to the ratio between said maximum input current value (IM) and the current gain (β) of the bipolar transistors of said pair on the common emitter node of said pair of bipolar transistors (Q3, Q4) and on the output nodes of said predistortion stages (Q1, Q2).
Claim 5
Dependent Claim
26 words
An analog multiplier according to claim 1, characterized by being a four-quadrant multiplier employing three pairs of emitter-coupled bipolar transistors according to a Gilbert cell configuration.
Claim 6
Dependent Claim
15 words
An analog multiplier according to claim 1, characterized by being configured for a single-ended output.
Claim 7
Independent Claim
98 words
A method of reducing the error on the output signal produced by an analog multiplier comprising at least a differential output stage composed of a pair of emitter-coupled bipolar transistors (Q3, Q4), each being driven by a predistortion stage (Q1, Q2) having an inverted hyperbolic tangent transfer function and an output node functionally connected to the base of the respective bipolar transistor of said pair, characterized by generating a current replica of the base current of the bipolar transistors of said pair and forcing said replica current on the output node of the respective predistortion stage (Q1, Q2).
Claim 8
Dependent Claim
37 words
A method according to claim 7, characterized by forcing a current inversely proportional to the current gain of the bipolar transistors (Q3, Q4) of said pair on the common emitter node of said pair of bipolar transistors.
Claim 9
Independent Claim
109 words
A method of reducing the error on the output signal produced by an analog multiplier composed of at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function and an output node functionally connected to the base of the respective bipolar transistor of said pair, characterized by forcing a current inversely proportional to the current gain of the bipolar transistors of said pair on the output nodes of said predistortion stages ((Q1, Q2) and on the common emitter node of said pair of bipolar transistors (Q3, Q4).
Claim 10
Dependent Claim
34 words
A method according to claim 8 or 9, characterized in that said current is equal to a preset maximum input current value divided by the current gain of the bipolar transistor of said pair.
References Cited (Backward Citations)
EP0157520A2
Cited
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