Disk array apparatus

Assignee: SK Hynix America Inc

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Filing: 1995-12-14

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Granted: —

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Expires: 2015-12-14

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Abstract

Abstract The invention provides for a high performance scalable hardware architecture for a disk array storage subsystem which supports RAID modes 0, 3, 4 and 5. The architecture features a high bandwidth parity calculation engine (132), a buffered PCI interface (130) operating at the full speed of a PCI bus (102), and a dedicated local memory (136). The dedicated local memory (136) is dual ported so that PCI and parity operations may operate concurrently. The architecture of the disk array controller allows parity calculations and memory block moves to occur without interfering with the controller processor or its associated memory, freeing the controller processor to manage array task control. The array controller configuration allows simultaneous operation of data block moves between storage I/O devices and local memory (136); data block moves between host SCSI connections and local memory; parity calculations; and normal CPU memory fetches, queued operations for block moves and queued operations for parity tasks. <IMAGE>

Inventors

👤 John W. Stewart
👤 Dennis E. Gates
👤 Rodney A. Dekoning
👤 Curtis W. Rink

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-11-01 12:40

CPC Classifications

G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G06F3/00; G06F3/06; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833

Claims Analysis

Total Claims: 4

Claim 1

Independent Claim 170 words

Disk array apparatus for operation with a host computer (12) and a plurality of disk drive means (114A-114E) comprising a first high speed local bus (102), an interface (104) connecting said first high speed local bus (102) with said host computer (12), at least one interface (112A-112E) connecting said plurality of disk drive means (114A-114E) with said first high speed local bus (102), and processor means (106) connected to said first high speed local bus (102) for controlling the operation of the components connected to said first high speed local bus, characterized by parity assist logic means (132) connected to said first high speed local bus (102), local data storage means (136), and a second high speed local bus (138) connecting said parity assist logic means (132) with said local storage means (136), wherein said parity assist logic means (132) is arranged to provide data via said second high speed local bus (138) to said local storage means (136) for the determination of parity data during disk array write operations.

Claim 2

Dependent Claim 66 words

Apparatus as claimed in Claim 1, wherein said parity assist logic means (132) comprises a parity assist engine (132), a dual ported memory interface (134) connecting said parity assist engine (132) with said local storage means (136) via said second high speed local bus (138), and an interface circuit (130) for connecting said dual ported memory interface (134) with said first high speed local bus (102).

Claim 3

Dependent Claim 16 words

Apparatus as claimed in Claim 2, wherein said parity assist engine (132) comprises an exclusive-OR circuit.

Claim 4

Dependent Claim 17 words

Apparatus as claimed in any one of Claims 1 to 3, and comprising a disk array controller.

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