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EP0710959A2
Expired / Lapsed
EP
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Semiconductor device equipped with simple stable switching circuit for selectively supplying different power voltages
Assignee: NEC Corp
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Filing: 1995-11-03
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Granted: —
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Expires: 2015-11-03
Abstract
Abstract An electrically erasable and programmable read only memory device is equipped with a supply voltage switching circuit (31) responsive to a write enable signal (WE) for selectively supplying a write-in voltage (Vpp) and a read-out voltage (Vcc) through a power distribution line (37) to a row address decoder unit (33), and the supply voltage switching circuit includes a series of first and second p-channel enhancement type transistors (Qp31/Qp32) having respective gate electrodes coupled to the write-in voltage line and the power distribution line, a third p-channel enhancement type transistor (Qp33) having a gate electrode coupled to the power distribution line and a controlling sub-circuit (31a) responsive to the write enable signal so as to supply first and second control signals (IN31/IN32) of the ground level and a third control signal (IN33) of the potential level equal to the power distribution line to the first and second p-channel enhancement type transistors and the third p-channel enhancement type transistor when the write enable signal is in the active level.
Inventors
- 👤 Tetsuya c/o NEC Corp. Ohtsuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:54
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C5/00; G11C5/14; G11C5/143; G11C16/30
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
488 words
A supply voltage switching circuit incorporated in a semiconductor integrated circuit device, comprising: a switching section coupled between a plurality of power supply lines (201-20n; Vpp/Vcc) and a power distribution line (21) for selectively coupling said plurality of power supply lines to said power distribution line, and a controlling sub-circuit (22; 31a) coupled to said switching section for controlling said switching section, characterized in that said switching section includes a plurality of first series sub-circuits (211-21n-1; 31b/31c) coupled said power distribution line (21) and a plurality of power supply lines (Vpp/Vcc) different in power voltages thereon, each of said plurality of first series sub-circuits including a first p-channel enhancement type transistor (Qp(1)/Qp(3)/Qp (2i-1)/ Qp(2n-3); Qp31; Qp31/Qp34) having a first source node (S) coupled to associated one of said plurality of power supply lines, a first gate electrode (G) and a first drain node (D) and a second p-channel enhancement type transistor (Qp(2)/Qp(4)/ Qp(2i)/Qp(2n-2); Qp32; Qp32/Qp33) having a second source node (S) coupled to said first drain node, a second gate electrode (G) and a second drain node (D) coupled to said power distribution line, and in that said controlling sub-circuit (22; 31a) is responsive to a selecting signal (SEL; WE) indicative of one of said plurality of power supply lines so as to producing a first control signal (IN1/IN3/IN2i-1/IN2i-3; IN31) of a first certain potential level (GND) lower than the power voltage on associated one of said plurality of power supply lines by a first threshold level of said first p-channel enhancement type transistor coupled to said one of said plurality of power supply lines, a second control signal (IN2/IN4/IN2i/IN2n-2; IN32/IN33) of a second certain potential level (GND) lower than a potential level on said power distribution line by a second threshold of said second p-channel enhancement type transistor associated with said one of said plurality of power supply lines, a third control signal (IN1/IN3/IN2i-1/IN2i-3; IN31) of a third certain potential level equal to the power voltage on each of the other or others of said plurality of power supply lines, and a fourth control signal (IN2/IN4/IN2i/IN2n-2; IN32/IN33) of a fourth certain potential level equal to the potential level on said power distribution line, said first control signal being supplied to said first gate electrode of said first p-channel enhancement type transistor coupled to said one of said plurality of power supply lines, said second control signal being supplied to said second gate electrode of said second p-channel enhancement type transistor associated with said one of said plurality of power supply lines, said third control signal being supplied to said first gate electrode of said first p-channel enhancement type transistor or transistors coupled to the other or others of said plurality of power supply lines, said fourth control signal being supplied to said second gate electrode of said second p-channel enhancement type transistor or transistors associated with said other or others of said plurality of power supply lines.
Claim 2
Dependent Claim
127 words
The supply voltage switching circuit as set forth in claim 1, in which one of said plurality of first series sub-circuits is replaced with a second series sub-circuit (21n; 31c) including a third p-channel enhancement type transistor (Qp(2n-1); Qp33) having a third source node (S) coupled to another power supply line (Vn; Vcc) of the lowest power voltage, a third gate electrode and a third drain node coupled to said power distribution line, said second control signal (IN2n-1; IN33) being supplied to said third gate electrode when said selecting signal is indicative of said lowest power supply line, said fourth control signal (IN2n-1; IN33) being supplied to said third gate electrode when said selecting signal is indicative of said one of said plurality of power supply lines.
Claim 3
Dependent Claim
28 words
The supply voltage switching circuit as set forth in claim 1, in which said first certain potential level and said second certain potential level are the ground level.
Claim 4
Dependent Claim
76 words
The supply voltage switching circuit as set forth in claim 1, in which said semiconductor integrated circuit device is an electrically erasable and programmable read only memory device, and said plurality of series sub-circuits (31b/31c) are coupled between a write-in voltage line (Vpp) and said power distribution line (37) and between a read-out voltage line (Vcc) and said power distribution line (37), respectively, said write-in voltage line higher in potential level than said read-out voltage line.
Claim 5
Dependent Claim
70 words
The supply voltage switching circuit as set forth in claim 2, in which said second series sub-circuit (31c) and the other of said plurality of first series sub-circuits (31b) are coupled between a write-in voltage line (Vpp) and said power distribution line (37) and between a read-out voltage line (Vcc) and said power distribution line (37), respectively, said write-in voltage line higher in potential level than said read-out voltage line.
Claim 6
Dependent Claim
123 words
The supply voltage switching circuit as set forth in claim 1, in which said controlling sub-circuit includes a plurality of switching units (221-22n-1) associated with said plurality of first series sub-circuits, each of said plurality of switching units having a first logic gate (INV1) powered by associated one of said plurality of power supply lines and a source of said first certain potential level and a second logic gate (INV2) powered by said power distribution line and a source of said second certain potential level, said first and second logic gates (INV1/INV2) being responsive to a signal bit of said selecting signal for producing said first control signal or said third control signal and said second control signal or said fourth control signal.
Claim 7
Dependent Claim
21 words
The supply voltage switching circuit as set forth in claim 6, in which said first and second logic gates are inverters.
Claim 8
Dependent Claim
28 words
The supply voltage switching circuit as set forth in claim 6, in which said first certain potential level and said second certain potential level are the ground level.
Claim 9
Dependent Claim
207 words
The supply voltage switching circuit as set forth in claim 2, in which said controlling sub-circuit includes a plurality of switching units (221-22n) associated with said second series sub-circuit (21n) and the other or others of said plurality of first series sub-circuits (211-21n-1), respectively, each of said plurality of switching units (221-22n-1) associated with said other or others of said plurality of first series sub-circuits having a first logic gate (INV1) powered by associated one of said plurality of power supply lines and a source of said first certain potential level and a second logic gate (INV2) powered by said power distribution line and a source of said second certain potential level, the switching unit (22n) associated with said second series sub-circuit having a third logic gate (INV3) powered by said source of said second certain potential level and said power distribution line, said first and second logic gates (INV1/INV2) being responsive to a signal bit of said selecting signal for producing said first control signal or said third control signal and said second control signal or said fourth control signal, said third logic gate (INV3) being responsive to another signal bit of said selecting signal for producing said second control signal or said fourth control signal.
Claim 10
Dependent Claim
22 words
The supply voltage switching circuit as set forth in claim 9, in which said first, second and third logic gates are inverters.
Claim 11
Dependent Claim
28 words
The supply voltage switching circuit as set forth in claim 9, in which said first certain potential level and said second certain potential level are the ground level.
References Cited (Backward Citations)
No citation records indexed.
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