Patent EP0707270A2 successfully refreshed from Google Patents.
EP0707270A2
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EP
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Method and apparatus for validating system operation
Assignee: International Business Machines Corp
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Filing: 1995-09-22
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Granted: —
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Expires: 2015-09-22
Abstract
Abstract A method and apparatus for providing system operation validation is disclosed. The method and apparatus for validation operates within a computer system comprising a central processing unit coupled to a programmable memory, and to a system device. The programmable memory may store programs and instructions executable on the CPU and a non-volatile memory is also provided for access by the CPU. The system operation validation is provided by a chip identifier located within a device memory within the system device, which memory also serves as a chip identifier register. Selected information stored within the non-volatile memory is used, along with the chip identifier, to generate a first encryption code associated with the system device. An encryption key is used to generate a second encryption code associated with the computer system. The first and second encryption codes are matched to provide a first level system operation validation. A second chip identifier is generated, which identifier is associated with the computer system. Both chip identifiers are compared to provide a second level system operation validation.
Inventors
- 👤 David O. Lewis
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 08:52
CPC Classifications
G; G06; G06F; G06F21/00; G06F21/50; G06F21/57; G06F21/10; G06F21/12; G06F21/121; G06F21/60; G06F21/64; G06F21/70; G06F21/71; G06F21/73; G06F2207/00; G06F2207/72; G06F2207/7219
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
137 words
In a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, a system device, coupled to said CPU, and a non-volatile memory, coupled to said CPU, a system operation validator comprising: a chip identifier located in a chip identifier register within said system device; means for utilizing selected information stored with said non-volatile memory and said chip identifier to generate a first encryption code associated with said system device; an encryption key stored within said programmable memory; means for generating a second encryption code associated with said CPU using said encryption key, wherein said encryption codes must match for system operation validation; means for generating a second chip identifier associated with said CPU, wherein said chip identifiers must match for system operation validation.
Claim 2
Dependent Claim
31 words
The invention according to claim 1 wherein said system device is a field-replaceable unit and said chip identifier is a chip serial number and said non-volatile memory is a semiconductor-type device.
Claim 3
Dependent Claim
38 words
The invention according to claim 1 wherein said chip identifier is a chip serial number and said non-volatile memory is a magnetic media-type device or an tape-drive device with said information being stored as microcode on a tape.
Claim 4
Dependent Claim
16 words
The invention according to claim 1 wherein said encryption codes are comprised of message authentication codes.
Claim 5
Dependent Claim
142 words
In a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, a system device, coupled to said CPU, and a non-volatile memory, coupled to said CPU, a method for validating system operation comprising the steps of: locating a chip identifier within in a chip identifier register within said system device; utilizing selected information stored with said non-volatile memory and said chip identifier to generate a first encryption code associated with said system device; generating a second encryption code associated with said CPU using a encryption key; determining whether said encryption codes match for system operation validation; upon matching said encryption codes, generating a second chip identifier associated with said CPU; determining whether said chip identifiers match for system operation validation; upon matching said chip identifiers, granting system operation.
Claim 6
Dependent Claim
49 words
The invention according to claim 5 wherein said system device is a field-replaceable unit and said chip identifier is a chip serial number and said non-volatile memory is an EPROM-type device or a DASD-type device or a tape-drive device with said information being stored as microcode on a tape.
Claim 7
Independent Claim
120 words
A system operation validator for use in granting system operation to a system device having a device memory and being coupled to an apparatus having a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, and a non-volatile memory, coupled to said CPU, said system operation validator comprising: means for utilizing selected information stored within said non-volatile memory and unique device information stored within said device memory to generate an encryption code associated with said system device; an encryption key stored within said programmable memory; means for generating a second encryption code associated with said CPU using said encryption key, wherein said encryption codes must match for system operation validation.
Claim 8
Dependent Claim
71 words
The invention according to claim 7 further comprising: a chip identifier located in a chip identifier register within said device memory; means for generating a second chip identifier associated with said CPU, wherein said chip identifiers must match for system operation validation, said encryption codes being comprised of message authentication codes ; and said means for matching said encryption codes further determining whether part of said select information has been altered.
Claim 9
Independent Claim
96 words
A method for validating system operation of a system device, which has a device memory, within a computer system comprising a central processing unit (CPU) coupled to a programmable memory, which may store programs and instructions executable on said CPU, and a non-volatile memory, coupled to said CPU, said method comprising the steps of: (a) generating a unique device digital signature associated with said system device; (b) generating a unique system digital signature associated with said computer system; (c) evaluating said unique digital signatures for validation; (d) upon validation, granting system operation to said system device.
Claim 10
Dependent Claim
138 words
The method according to claim 9 wherein said step of generating a unique device digital signature associated with said system device includes the steps of: locating a chip identifier within a chip identifier register; utilizing selected information stored with said non-volatile memory and said chip identifier to generate a device encryption code associated with said system device ; said step of generating a unique system digital signature associated with said computer system including the step of generating a system encryption code associated with said CPU using an encryption key ; said step of evaluating said unique digital signatures for validation including the steps of: determining whether said encryption codes match for system operation validation; upon matching said encryption codes, generating a second chip identifier associated with said CPU; determining whether said chip identifiers match for system operation validation.
Claim 11
Dependent Claim
51 words
The invention according to claim 9 wherein said step of evaluating said unique digital signatures for validation includes the step of determining whether part of select information stored within either said system device or said computer system has been altered ; and said encryption codes are comprised of message authentication codes.
References Cited (Backward Citations)
No citation records indexed.
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