Patent EP0707256A2 successfully refreshed from Google Patents.
EP0707256A2
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EP
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Circuit for placing a cache memory into low power mode in response to special bus cycles
Assignee: Compaq Computer Corp
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Filing: 1995-10-13
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Granted: —
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Expires: 2015-10-13
Abstract
Abstract A circuit is described for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by a microprocessor. In particular, the special cycles may be the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.
Inventors
- 👤 Jens K. Ramsey
- 👤 Michael E. Tubbs
- 👤 Jeffrey C. Stevens
- 👤 Charles J. Stancil
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 17:50
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3228; G06F1/3234; G06F1/324; G06F1/325; G06F1/3268; G06F1/3275; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0811; G06F12/0815; G06F12/0831; G06F12/0833; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; G06F2212/00; G06F2212/10; G06F2212/1028; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
126 words
A circuit for placing a cache memory device located in a computer system into a low power state, wherein the computer system includes a bus, a microprocessor coupled to the bus, and a main memory coupled to the bus, and wherein the cache memory device is coupled to the bus, the circuit comprising: means coupled to the bus for detecting a special cycle on the bus; means coupled to said detecting means for asserting a first signal if said special cycle is detected, wherein said special cycle is generated by the microprocessor to indicate that the microprocessor is entering into low power consumption mode; and means responsive to said first signal and coupled to the bus for placing the cache memory device into low power mode.
Claim 2
Dependent Claim
159 words
The circuit of claim 1, for use with a cache memory device which includes a first address strobe input and a chip select input, wherein said means for placing the cache memory device into low power mode includes: means responsive to said first signal and coupled to the bus for providing a cache address strobe signal to said address strobe input of the cache memory device, said cache address strobe signal providing means asserting said cache address strobe signal if said first signal is asserted; and means responsive to said first signal and coupled to the bus for providing a chip select signal to said chip select input of the cache memory device, said chip select signal providing means deasserting said chip select signal if said first signal is asserted, wherein the cache memory device is placed into the low power state in response to said cache address strobe signal being asserted and said chip select signal being deasserted.
Claim 3
Dependent Claim
97 words
The circuit of claim 1, for use with a cache memory device which includes a chip select input, wherein said means for placing the cache memory device into low power mode includes: means responsive to said first signal and coupled to the bus for providing a chip select signal to said chip select input of the cache memory device, said chip select signal providing means deasserting said chip select signal if said first signal is asserted, wherein the cache memory device is placed into the low power state in response to said chip select signal being deasserted.
Claim 4
Dependent Claim
31 words
A computer system, comprising: a bus; a cache memory device coupled to said bus; a microprocessor coupled to said bus; and a circuit according to any of claims 1 to 3.
Claim 5
Dependent Claim
18 words
The computer system of claim 4, wherein said cache memory device is a synchronous static random access memory.
Claim 6
Dependent Claim
16 words
The computer system of claim 4 or claim 5, wherein said microprocessor is a Pentium processor.
Claim 7
Dependent Claim
17 words
The computer system of claim 4 or claim 5, wherein said microprocessor is a 486 DX4 processor.
Claim 8
Dependent Claim
31 words
The computer system of any of claims 4 to 7, when dependent on claim 2, wherein said cache memory device includes a first address strobe input and a chip select input.
Claim 9
Dependent Claim
302 words
The computer system of claim 8, further comprising: a main memory coupled to said bus; means coupled to said bus for generating a snoop cycle having a snoop address on said bus, wherein said cache memory device further includes a second address strobe input, wherein said microprocessor includes an internal cache, wherein said microprocessor is able to respond to said snoop cycle while said microprocessor is in its low power consumption mode, wherein said microprocessor generates a writeback cycle to said main memory if said snoop address corresponds to a modified location in said internal cache, wherein said microprocessor asserts a processor address strobe signal to initiate said writeback cycle, said processor address strobe signal being provided to said second address strobe input of said cache memory device, wherein asserting said processor address strobe signal causes said cache memory device to come out of low power state if said cache memory device was previously in low power state, and wherein said circuit further includes: means responsive to said first signal for providing a second signal indicating that said cache memory device is in low power state, said second signal being maintained in an asserted state in response to said first signal being asserted; means coupled to said bus for detecting for the completion of said writeback cycle; and means responsive to said second signal and coupled to said writeback cycle detecting means for asserting a third signal if said second signal is asserted and said writeback cycle is completed, wherein said cache address strobe signal providing means and said chip select signal providing means are further responsive to said third signal, said cache address strobe signal being asserted and said chip select signal being deasserted if said third signal is asserted for placing said cache memory device back into low power state.
Claim 10
Dependent Claim
303 words
The computer system of claim 8, further comprising: a main memory coupled to said bus; means coupled to said bus for generating a snoop cycle having a snoop address on said bus; means coupled to said bus for determining if said snoop address is in said cache memory device; means coupled to said determining means for asserting a second signal if said snoop address corresponds to a modified location in said cache memory device; and means responsive to said second signal and coupled to said bus for generating a writeback cycle to said main memory if said second signal is asserted, wherein said cache address strobe signal providing means is further responsive to said second signal, said cache address strobe signal being asserted if said second signal is asserted, wherein asserting said cache address strobe signal causes said cache memory device to transition out of low power state if said cache memory device was previously in low power state, and wherein said circuit further includes: means responsive to said first signal for providing a third signal indicating that said cache memory device is in low power state, said third signal being maintained in an asserted state in response to said first signal being asserted; means coupled to said bus for detecting for the completion of said writeback cycle; and means responsive to said third signal and coupled to said writeback cycle detecting means for asserting a fourth signal if said third signal is asserted and said writeback cycle is completed, wherein said cache address strobe signal providing means and said chip select signal providing means are further responsive to said fourth signal, said cache address strobe signal being asserted and said chip select signal being deasserted if said fourth signal is asserted for placing said cache memory device back into low power state.
Claim 11
Dependent Claim
25 words
The computer system of any of claims 4 to 7, when dependent on claim 3, wherein said cache memory device includes a chip select input.
Claim 12
Dependent Claim
246 words
The computer system of claim 11, further comprising: a main memory coupled to said bus; and means coupled to said bus for generating a snoop cycle having a snoop address on said bus, wherein said cache memory device includes an address strobe input, wherein said microprocessor includes an internal cache, wherein said microprocessor is able to respond to said snoop cycle while said microprocessor is in its low power consumption mode, wherein said microprocessor generates a writeback cycle to said main memory if said snoop address corresponds to a modified location in said internal cache, wherein said chip select signal providing means is further responsive to said writeback cycle, said chip select signal being asserted if said writeback cycle is active, wherein asserting said chip select signal causes said cache memory device to transition out of low power state if said cache memory device was previously in low power state, and wherein said circuit further includes: means responsive to said first signal for providing a second signal indicating that said cache memory device is in low power state, said second signal being maintained in an asserted state in i response to said first signal being asserted, wherein i said chip select signal providing means is further responsive to said second signal, said chip select signal being deasserted if said second signal is asserted and said writeback cycle has completed, and wherein deasserting said chip select signal places said cache memory device back into low power state.
Claim 13
Dependent Claim
247 words
The computer system of claim 11, further comprising: means coupled to said bus for generating a snoop cycle having a snoop address on said bus; means coupled to said bus for determining if said snoop address is in said cache memory device; means coupled to said determining means for asserting a second signal if said snoop address corresponds to a modified location in said cache memory device; and means responsive to said second signal and coupled to said bus for generating a writeback cycle to said main memory if said second signal is asserted, wherein said chip select signal providing means is further responsive to said writeback cycle, said chip select signal providing means asserting said chip select signal if said writeback cycle is active, wherein asserting said chip select signal causes said cache memory device to transition out of low power state if said cache memory device was previously in low power state, and wherein said circuit further includes: means responsive to said first signal for providing a third signal indicating that said cache memory device is in low power state, said third signal being maintained in an asserted state in response to said first signal being asserted, wherein said chip select signal means is further responsive to said third signal, said chip select signal being deasserted if said third signal is asserted and said writeback cycle has completed, and wherein deasserting said chip select signal places said cache memory device back into low power state.
Claim 14
Dependent Claim
21 words
The computer system of any of claims 4 to 7, wherein said special cycle includes a stop grant acknowledge special cycle.
Claim 15
Dependent Claim
100 words
The computer system of claim 14, wherein said computer system further includes means for asserting a stop clock signal if said computer system has been idle for a predetermined period of time, wherein said microprocessor includes a stop clock input for receiving said stop clock signal, wherein said microprocessor further includes a clock input, said stop clock signal being a request to slow down or stop said clock input to place said microprocessor into low power consumption mode, and wherein said microprocessor generates said stop grant acknowledge cycle on said bus in response to assertion of said stop clock signal.
Claim 16
Dependent Claim
58 words
The computer system of any of claims 4 to 7, wherein said special cycle is a halt special cycle, and wherein said microprocessor generates said halt special cycle on said bus if said microprocessor executes a halt instruction, said halt instruction causing operation of said microprocessor to cease and to place said microprocessor into low power consumption mode.
References Cited (Backward Citations)
US4980836A
Cited
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