Semiconductor memory device with synchronous dram whose speed grade is not limited

Assignee: NEC Corp

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Filing: 1995-09-27

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Granted: —

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Expires: 2015-09-27

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Abstract

Abstract The semiconductor memory device disclosed includes a burst counter (2) in a first stage (36) of pipeline, a column switch latch portion (4) in a second stage (37) of the pipeline and an output data latch circuit (8) in a third stage (38). In the operation mode with CAS latency of 2, as a control signal of the burst counter (2), a clock signal is outputted and, as a control signal of the column switch latch portion (4), a logical sum OR (11) fixed to a high level by a mode signal is outputted. The device further includes a delay circuit (13) and an output controller (14, 15, 16). The data output circuit is arranged such that it supplies, as a control signal of the output data latch circuit (8), a logical product AND (15) of the inversion of the mode signal and the clock signal, and a logical sum OR (16) of a signal delayed through the delay circuit (13) and a logical product AND (14) of the mode signal. In the synchronous DRAM thus configured, the speed grade in the operation mode with CAS latency of 2 is not restricted.

Inventors

👤 Yasuhiro C/O Nec Corporation Takai

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-31 21:12

CPC Classifications

G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1072; G11C7/1015; G11C7/1039

Claims Analysis

Total Claims: 3

Claim 1

Independent Claim 358 words

A semiconductor memory device which includes a burst counter (2) for latching an external address signal (A1) and generating an internal address signal (A1, A2, A3, ...) in synchronism to a first clock signal having a predetermined cycle period; a column decoder (3) for decoding the internal address signal (A1, A2, A3, ...); a column switch latch portion (4) which assumes a data-through state with the supply of the first clock signal being cut-off when a mode signal internally supplied is active, and latches the output of the column decoder (3) in synchronism to the first clock signal when the mode signal is inactive; and an output data latch circuit (8) for reading out memory data designated by the output of the column switch latch portion (4) under control of a read command and latching the read-out data in synchronism to the first clock signal, and in which, when the mode signal is inactive, a first operation mode is set to read out the data designated by the internal address signal in synchronism to the first clock signal that is N (N being an integer not less than 2) clock cycles after the latch timing of the burst counter (2), and the read-out data is outputted from the output data latch circuit (8), and when a second clock signal having a longer cycle period than the first clock signal is supplied in lieu of the first clock signal and also when the mode signal is inactive, a second operation mode is set to read out the data designated by the internal address signal in synchronism to the second clock signal N-1 clock cycles after the latch timing of the burst counter (2), and the read-out data is outputted from the output data latch circuit, said semiconductor memory device characterized by comprising: a delay circuit (13) for delaying said second clock signal by a predetermined period of time under said second operation mode; and an output control means (14, 15, 16) for controlling the data to be outputted from said output data latch circuit (8) in synchronism to said second clock signal that is delayed by said delay circuit.

Claim 2

Dependent Claim 82 words

The semiconductor memory device according to claim 1, in which said output control means is arranged such that it supplies, as a control signal of said output data latch circuit (8), a logical product AND (15) of the inversion of said mode signal and the second clock signal, and a logical sum OR (16) of a signal obtained as a result of delaying said second clock signal through said delay circuit (13) and a logical product AND (14) of said mode signal.

Claim 3

Dependent Claim 49 words

The semiconductor memory device according to claim 2, in which said delay circuit (13) is arranged such that the time of delay determined thereby does not exceed the time determined as the difference between the cycle of said first clock signal and the cycle of said second clock signal.

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