Patent EP0703668A2 successfully refreshed from Google Patents.
EP0703668A2
Expired / Lapsed
EP
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Self-resetting CMOS multiplexer with static output driver
Assignee: International Business Machines Corp
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Filing: 1995-08-16
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Granted: —
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Expires: 2015-08-16
Abstract
Abstract Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and compliment input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or compliment input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An invertor tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output. The state of the select signal and of the input signals may be latched in the input circuit for proper pulse alignment.
Inventors
- 👤 Antonio Raffaele Pelella
- 👤 Yuen Hung Chan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 09:10
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356147; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/693
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
236 words
A multiplex circuit comprising: an input circuit, having true and complement inputs and a select input and true and compliment outputs; an output circuit having true and compliment inputs and an output and comprising a data latch responsive to a first latch signal to assume a first latch state and responsive to a second latch signal to assume a second latch state; the true and compliment outputs of the input circuit connected to the true and compliment inputs, respectively, of the output circuit; the output circuit further comprising a first latch control gate connected to the latch and to one of the true and compliment outputs and a second latch control gate connected to the latch and to the other of the true and compliment outputs and a first output gate connected to the output terminal of the output circuit and to one of the true and compliment outputs and a second output gate connected to the output terminal of the output circuit and connected to the other of the true and compliment outputs, the first and second latch control gates responsive to signals on the true and compliment outputs to generate first and second latch signals, respectively, and the first and second output gates responsive to true and compliment signals on the true and compliment outputs to produce an output signal on the output of the output circuit independent of the operation of the latch.
Claim 2
Dependent Claim
43 words
The multiplex circuit in accordance with Claim 1 and wherein the output circuit comprises an additional output gate connected in parallel with the first output gate to establish and maintain a desired output signal level at the output terminal of the output circuit.
Claim 3
Dependent Claim
91 words
The circuit in accordance with Claim 2 wherein the input circuit comprises first and second pairs of complimentary input gates connected to the true and compliment inputs of the input circuit and a pair of control gates connected to the control input and a pair of output gates, wherein the control gates are connected in series between the input terminals and output terminals of the input circuits, the input circuit further comprising a latch for maintaining a state of the outputs of the input circuit after termination of an input signal.
Claim 4
Dependent Claim
47 words
The circuit in accordance with claim 2 and wherein the output circuit further comprises a pair of series connected CMOS gates each having a gate terminal connected to one of the inputs of the output circuit and operative to control the state of the additional output gate.
Claim 5
Dependent Claim
93 words
The circuit in accordance with Claim 4 and wherein the output circuit further comprises an invertor tree comprising a pair of series connected P-channel MOS gates connected in series with a pair of series connected N-channel MOS gates at an interconnecting node connected to the output of the output circuit, and a reset terminal, the output circuit responsive to a reset signal on the reset terminal to reset the data latch, the invertor tree operative to retain the state of the output of the output circuit after the resetting of the data latch.
Claim 6
Dependent Claim
87 words
The circuit in accordance with claim 4 series connected wherein one of the P-channel gates has a gate terminal connected to one of the single true and compliment outputs and wherein the other of the P-channel gates has a gate terminal connected to one side of the data latch and to the gate terminal of one of the N-channel gates of the invertor tree, the other of the N-channel gates of the invertor tree having a gate terminal connected to the pair of series connected CMOS gates.
Claim 7
Dependent Claim
101 words
The circuit in accordance with Claim 6 and wherein the output circuit comprises a reset terminal and a voltage source terminal and a ground terminal and first and second N-channel MOS gates connected between the ground terminal and the true and compliment inputs, respectively, each of the N-channel MOS gates having a gate input connected to the voltage source terminal and operative to provide a low current drain to ground and to assure that the true and compliment input terminals of the output circuit remain at a ground level after a reset signal on the reset input terminal has been terminated.
Claim 8
Dependent Claim
67 words
The circuit in accordance with Claim 7 and wherein the output circuit further comprises a test latch and a first test input gate responsive to a first control signal and a test input signal for latching the test input signal in the test latch and a second test gate responsive to a second control signal to latch the state of the test latch in the data latch.
Claim 9
Dependent Claim
49 words
The circuit in accordance with Claim 8 wherein the input circuit comprises a control latch responsive to a select control signal to latch the state of the select control signal and to enable the input circuit to receive signals on the true and compliment inputs of the input circuit.
Claim 10
Dependent Claim
34 words
The circuit in accordance with Claim 9 wherein the input circuit further comprises first and second input latches for latching the state of pulses on the true and compliment inputs of the input circuit.
Claim 11
Dependent Claim
80 words
The circuit in accordance with Claim 10 wherein the input circuit further comprises first and second input gates connected to the true and compliment inputs of the input circuit and the true and compliment outputs of the input circuit and operative in parallel with the first and second input latches, respectively, whereby the first and second input gates are operative to initiate an output signal for the input circuit independent of the operation of the first and second input latches.
Claim 12
Dependent Claim
59 words
The circuit in accordance with Claim 10 wherein the first and second input latches are connected to the reset input of the input circuit and further comprising first and second current supply gates connected to the first and second input latches, respectively, for maintaining the first and second latches in a reset condition after termination of a reset pulse.
Claim 13
Dependent Claim
50 words
The circuit in accordance with Claim 11 wherein the input circuit further comprises first and second P-channel MOS gates having a gate terminal connected to ground to maintain internal nodes of the circuit at a predefined level to prevent activation of the circuit in response to short duration noise spikes.
Claim 14
Dependent Claim
37 words
The circuit in accordance with Claim 12 wherein the input circuit further comprises a by-pass gate connected to the select input of the input circuit to enable the circuit independent of the operation of the select latch.
Claim 15
Dependent Claim
23 words
The circuit in accordance with Claim 1 and further comprising a reset chain generating a reset pulse for asynchrously resetting the input circuit.
Claim 16
Dependent Claim
42 words
The circuit in accordance with claim 15 wherein the reset chain generates an additional reset pulse a predetermined period of time after the reset pulse for resetting the input circuit and the additional reset pulse is operative to reset the output circuit.
Claim 17
Independent Claim
83 words
A method of converting input pulses representing output signals of a plurality of circuits providing short duration output pulses to relatively longer duration output pulses for logic circuits requiring relatively longer duration input signals, the method comprising the steps of multiplexing a plurality of the input pulses under control of select pulses and storing individual ones of the multiplexed input pulses in a data latch and concomitantly providing an output pulse representative of the input pulse, independent of the operation of the latch.
Claim 18
Dependent Claim
31 words
The method in accordance with Claim 17 further comprising the step of resetting the data latch and maintaining the state of the output pulse after the resetting of the data latch.
Claim 19
Dependent Claim
45 words
The method in accordance with Claim 18 wherein short duration input pulses are intended to be received in coincidence with a select signal and further comprising the step of latching the select signal to control overlap of the select signal with short duration input signals.
Claim 20
Dependent Claim
30 words
The method in accordance with Claim 19 and further comprising the steps of latching input signals in the input circuit to assure coincidence of input signals with the select signal.
Claim 21
Dependent Claim
33 words
The method in accordance with Claim 20 and further comprising the step of generating output pulses from the input pulses upon arrival of input signals independent of the latching of the input signals.
References Cited (Backward Citations)
No citation records indexed.
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