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EP0702372A2
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A voltage reference for a ferroelectric IT/IC based memory
Assignee: Ramtron International Corp
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Filing: 1995-07-18
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Granted: —
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Expires: 2015-07-18
Abstract
Abstract A reference cell for a 1T-1C memory is disclosed for use in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM® mode. In a first embodiment, one of the reference cell capacitors is poled. In a second embodiment, the reference cell capacitors are not poled and maintain the same polarization state, thus reducing fatigue.
Inventors
- 👤 designation of the inventor has not yet been filed The
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 02:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
95 words
A reference cell for use in a ferroelectric memory including an array of 1T-1C memory cells, the reference cell comprising: first and second voltage reference outputs each coupled to a bit line in the array; first and second ferroelectric capacitors; means for coupling the first and second ferroelectric capacitors to the first and second voltage reference outputs; means for establishing a charge on one of the ferroelectric capacitors; and means for equally distributing the charge across both of the ferroelectric capacitors to create a substantially equal reference voltage on both of the voltage reference outputs.
Claim 2
Dependent Claim
28 words
A reference cell as in claim 1 in which the means for establishing a charge on one of the ferroelectric capacitors includes means for poling the ferroelectric capacitor.
Claim 3
Dependent Claim
29 words
A reference cell as in claim 2 in which the reference voltage is substantially half of the voltage generated by a memory cell when read in a non-volatile mode.
Claim 4
Dependent Claim
31 words
A reference cell as in claim 1 in which the means for establishing a charge on one of the ferroelectric capacitors includes means for writing a voltage to the ferroelectric capacitor.
Claim 5
Dependent Claim
29 words
A reference cell as in claim 2 in which the reference voltage is substantially half of the voltage generated by a memory cell when read in a dynamic mode.
Claim 6
Dependent Claim
27 words
A reference cell as in claim 1 in which the value of each of the ferroelectric capacitors is equal to the value of a memory cell capacitor.
Claim 7
Dependent Claim
53 words
A reference cell as in claim 1 in which the means for coupling the first and second ferroelectric capacitors to the reference outputs comprises a pair of transistors each having a current path coupled between a capacitor and a corresponding reference output, each transistor having a control node for receiving a control signal.
Claim 8
Dependent Claim
48 words
A reference cell as in claim 2 in which the means for poling one of the ferroelectric capacitors comprises a transistor having a current path coupled between the ferroelectric capacitor and a first control signal source, the transistor having a control node for receiving a second control signal.
Claim 9
Dependent Claim
196 words
A reference cell for use in a ferroelectric memory including an array of 1T-1C memory cells, the reference cell comprising: first and second voltage reference outputs each coupled to a corresponding bit line; first and second ferroelectric capacitors; first and second transistors each having a current path for coupling a first end of the first and second ferroelectric capacitors to the first and second voltage reference outputs, each transistor further including a control node for receiving a first control signal, wherein a second end of the first capacitor receives a second control signal and a second end of the second capacitor is coupled to ground; a third transistor having a current path coupled between the first end of the first capacitor and a source of a third control signal, the third transistor having a control node for receiving a fourth control signal; a fourth transistor having a current path coupled between the first end of the second capacitor and ground, the fourth transistor having a control node for receiving the fourth control signal; and a fifth transistor having a current path coupled between the reference outputs and a control node for receiving a fifth control signal.
Claim 10
Independent Claim
85 words
A method of generating a pair of substantially equal reference voltages at first and second voltage reference outputs for use in a ferroelectric memory including an array of 1T-1C memory cells, the method comprising the steps of: coupling first and second ferroelectric capacitors to the first and second voltage reference outputs; establishing a charge on one of the ferroelectric capacitors; and equally distributing the charge across both of the ferroelectric capacitors to create a substantially equal reference voltage on both of the voltage reference outputs.
Claim 11
Dependent Claim
118 words
A reference cell for use in a ferroelectric memory including an array of 1T-1C memory cells, the reference cell comprising: first and second voltage reference outputs each coupled to a bit line; first and second ferroelectric capacitors; means for writing a voltage to both of the ferroelectric capacitors such that the direction of the polarization vector of the ferroelectric capacitors is never changed; means for removing the developed charge from one of the capacitors; means for equally distributing the charge across both of the ferroelectric capacitors; and means for coupling the first and second ferroelectric capacitors to the first and second voltage reference outputs to create a substantially equal reference voltage on both of the voltage reference outputs.
Claim 12
Dependent Claim
193 words
A reference cell for use in a ferroelectric memory including an array of 1T-1C memory cells, the reference cell comprising: first and second voltage reference outputs each coupled to a bit line; first and second ferroelectric capacitors; first and second transistors each having a current path for coupling a first end of the first and second ferroelectric capacitors to the first and second voltage reference outputs, each transistor further including a control node for receiving a first control signal, wherein a second end of the first capacitor and second capacitors is coupled to ground; fourth and fifth transistors each having a current path coupled between a source of supply voltage and the first end of the first and second ferroelectric capacitors, respectively, each transistor further including a control node for receiving a second control signal; a fifth transistor having a current path coupled between the first end of one of the ferroelectric capacitors and ground, the transistor having a control node for receiving a third control signal; and a sixth transistor having a current path coupled between first ends of the ferroelectric capacitors and a control node for receiving a fourth control signal.
Claim 13
Independent Claim
107 words
A method of generating a pair of substantially equal reference voltages at first and second voltage reference outputs for use in a ferroelectric memory including an array of 1T-1C memory cells, the method comprising the steps of: writing a voltage to a pair of ferroelectric capacitors such that the direction of the polarization vector of the ferroelectric capacitors is never changed; removing the developed charge from one of the capacitors; equally distributing the charge across both of the ferroelectric capacitors; and coupling the ferroelectric capacitors to the first and second voltage reference outputs to create a substantially equal reference voltage on both of the voltage reference outputs.
Claim 14
Dependent Claim
32 words
The method of claim 10 further comprising the step of decoupling the ferroelectric capacitors from the first and second voltage reference outputs after a pair of corresponding memory cells has been restored.
Claim 15
Dependent Claim
54 words
A ferroelectric memory comprising: an array of 1T-1C ferroelectric memory cells arranged in rows and columns, each row of memory cells having an associated bit line; a column of ferroelectric reference cells each having two outputs for providing substantially equal reference voltages, wherein the two outputs are coupled to a pair of bit lines.
Claim 16
Dependent Claim
18 words
A ferroelectric memory as in claim 15 in which the array is configured in an open memory architecture.
Claim 17
Dependent Claim
18 words
A ferroelectric memory as in claim 15 in which the array is configured in a folded memory architecture.
Claim 18
Dependent Claim
34 words
A ferroelectric memory as in claim 15 in which the reference cell includes two ferroelectric capacitors each having a value equal to the value of a ferroelectric capacitor in one of the memory cells.
Claim 19
Dependent Claim
44 words
A ferroelectric memory as in claim 18 in which the reference cell further comprises: means for establishing a charge on one of the ferroelectric capacitors; and means for sharing the charge between the two ferroelectric capacitors to establish the two substantially equal reference voltages.
Claim 20
Dependent Claim
37 words
A ferroelectric memory as in claim 15 in which a load capacitance associated with each of the memory cell bit lines is substantially equal to a load capacitance associated with each of the reference cell bit lines.
References Cited (Backward Citations)
US4873664A
Cited
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