Patent EP0699912A2 successfully refreshed from Google Patents.
EP0699912A2
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EP
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An apparatus, method, and wafer used for testing integrated circuits formed on a product wafer
Assignee: Motorola Solutions Inc
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Filing: 1995-08-17
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Granted: —
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Expires: 2015-08-17
Abstract
Abstract A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.
Inventors
- 👤 Robert Keith Dehaven
- 👤 James F. Wenzel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 09:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07314; G01R31/2832; G01R31/2836; G01R31/2849; G01R31/282; G01R31/2831; G01R31/2872; G01R31/2874; G01R31/2879; G01R31/2881; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49128; Y10T29/49155; Y10T29/49162
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
66 words
A test apparatus comprising: a semiconductor product wafer (14) comprising integrated circuits; a circuit distribution wafer (16); and a compliant interconnect media (18) for coupling the semiconductor product wafer to the circuit distribution wafer wherein circuitry (36a & 34a) on the circuit distribution wafer is designed to provide electrical stimulus to circuitry on the semiconductor product wafer via electrical signals transmitted through the compliant interconnect media.
Claim 2
Dependent Claim
232 words
A test apparatus comprising: a semiconductor product wafer comprising a plurality of N integrated circuits where N is a positive finite integer, each integrated circuit within the plurality of N integrated circuits having circuitry which is interconnected by a plurality of conductive interconnections, a portion of the plurality of conductive interconnections forming a top conductive layer of each integrated circuit in the plurality of N integrated circuits; a circuit distribution wafer comprising a plurality of circuits, the plurality of circuits comprising a plurality of N stimulus circuits wherein at least one stimulus circuit is coupled to electrically stimulate at least one integrated circuit in the plurality of N integrated circuits, the plurality of circuits on the circuit distribution wafer also comprising M circuit modules, where M is a finite positive integer, the M circuit modules being used for providing feedback information regarding a stimulating of the plurality of N integrated circuits by the plurality of N stimulus circuits, the plurality of N stimulus circuits having a top conductive layer; and a compliant interconnect media having a plurality of conductive interconnects for coupling the top conductive layer of the circuit distribution wafer to the top conductive layer of the semiconductor product wafer wherein the N stimulus circuits on the circuit distribution wafer stimulus circuitry stimulate the N integrated circuits on the semiconductor product wafer via electrical signals transmitted through the compliant interconnect media.
Claim 3
Dependent Claim
277 words
A semiconductor wafer test apparatus comprising: a semiconductor product wafer comprising a plurality of N integrated circuits where N is a positive finite integer, each integrated circuit within the plurality of N integrated circuits having circuitry which is interconnected by a plurality of conductive interconnections, a portion of the plurality of conductive interconnections forming a top conductive layer of each integrated circuit in the plurality of N integrated circuits; a circuit distribution semiconductor wafer comprising a plurality of circuits, the plurality of circuits comprising a plurality of N test circuits wherein at least one of the N test circuits is electrically designed to test at least one integrated circuit in the plurality of N integrated circuits, the plurality of circuits also comprising M circuit modules, where M is a finite positive integer, the M circuit modules being used for providing feedback information regarding a testing of the plurality of N integrated circuits by the plurality of N test circuits, the circuit distribution semiconductor wafer having a plurality of external connection terminals for coupling the circuit distribution semiconductor wafer to an external controller, the plurality of N test circuits having a top conductive layer; and an interconnect media located between the semiconductor product wafer and the circuit distribution semiconductor wafer which has a plurality of conductive interconnects encapsulated in an elastomer material, the interconnect media being used to couple the top conductive layer of the circuit distribution semiconductor wafer to the top conductive layer of the semiconductor product wafer wherein the N test circuits on the circuit distribution semiconductor wafer test the N integrated circuits on the semiconductor product wafer via electrical signals transmitted through the interconnect media.
Claim 4
Dependent Claim
119 words
A stimulus apparatus for stimulating a product wafer, the stimulus apparatus comprising: a chamber for holding both the product wafer comprising a plurality of product integrated circuits and having a top conductive layer and a stimulus wafer comprising a plurality of stimulus circuits and having a top conductive layer, the chamber holding the product wafer and the stimulus wafer such that the top conductive layer of the product wafer is facing the top conductive layer of the stimulus wafer, the chamber allowing the top conductive layers to be electrically coupled together via a compliant interconnect media. a first housing portion comprising means for heating/cooling the product wafer; and a second housing portion comprising means for heating/cooling the stimulus wafer.
Claim 5
Dependent Claim
118 words
A stimulus apparatus comprising: a chamber having at least one wafer holding means for holding both a product wafer and a test wafer wherein the product wafer and test wafer are electrically coupled together by a compliant interconnect media; means for altering a temperature of the product wafer, the means for altering being connected to the chamber; and a test controller coupled to the chamber via cabling, the test controller comprising: (a) a power supply unit; (b) a temperature unit for monitoring the temperature of the product wafer; (c) a function unit for providing test data to the product wafer through the test wafer; and (d) an analysis unit for analyzing test data received from the test wafer.
Claim 6
Dependent Claim
103 words
A semiconductor stimulus wafer (16) comprising: a plurality of stimulus circuits (34) wherein each stimulus circuit in the plurality of stimulus circuits is coupled to at least one exposed conductive contact region; at least one performance feedback circuit (36c); a plurality of input/output terminals (32b); a conductive bus (Fig. 4) coupling the plurality of input/output terminals to both the plurality of stimulus circuits and the at least one performance feedback circuit; and compliant interconnection means (18) coupled to the at least one exposed conductive contact region to allow the semiconductor stimulus wafer to be coupled to a wafer which comprises production integrated circuits.
Claim 7
Independent Claim
197 words
A method for forming a stimulus wafer, the stimulus wafer being formed for stimulating a semiconductor product wafer, the method for forming the stimulus wafer comprising: providing a substrate having a surface; forming, on the substrate in a first area, a plurality of input/output terminals for communication of information to and from the stimulus wafer; forming, on the substrate in a second area different from the first area, a plurality of driver circuits, the plurality of driver circuits being laid out in a predetermined two-dimensional geometry across the surface of the substrate, the plurality of driver circuits comprising circuitry for controlling voltage, circuitry for controlling current, and circuitry for controlling signals through the plurality of driver circuits; forming at least one feedback circuit, on the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising temperature monitoring circuitry and performance monitoring circuitry for identifying which circuits in the plurality of driver circuits have identified a stimulus problem; forming a stimulus water conductive interconnect network for coupling signals between the plurality of input/output terminals, the plurality of driver circuits, and the at least one feedback circuit.
Claim 8
Independent Claim
173 words
A method for stimulating a product wafer using a stimulus wafer, the method comprising the steps of: providing the product water wherein the product wafer comprises a plurality of product integrated circuits which are to be stimulated, the product water having a selectively exposed top conductive layer of material coupled to the product integrated circuits; providing the stimulus water wherein the stimulus water comprises a plurality of stimulus circuits wherein at least one stimulus circuit within the plurality of stimulus circuits corresponds to one product integrated circuit within the plurality of product integrated circuits, the stimulus wafer having a selectively exposed top conductive layer of material coupled to the stimulus circuits; and positioning a compliant interconnect media between product wafer and the stimulus wafer, the compliant interconnect media coupling the selectively exposed top conductive layer of material of the product wafer with the selectively exposed top conductive layer of material of the stimulus wafer to allow the stimulus wafer to stimulate the product wafer via electrical signals transmitted through the compliant interconnect media.
Claim 9
Dependent Claim
188 words
A test circuit comprising: a first plurality of input terminals and a first plurality of output terminals; a plurality of buffers coupled between the first plurality of input terminals and the first plurality of output terminals, a portion of the first plurality of output terminals being coupled to a compliant interconnect media; a current sensing and blocking circuit for sensing current through one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined current limit is exceeded; a voltage sensing and blocking circuit for sensing voltage through the one of the first plurality of inputs and electrically disconnecting the one of the first plurality of inputs from the compliant interconnect media if a predetermined voltage limit is exceeded; a feedback circuit for receiving data from at least one of the voltage sensing and blocking circuit, the current sensing and blocking circuit, and the plurality of buffers, and using this data to provide test information; a temperature circuit coupled to the feedback circuit, the temperature circuit being used for receiving and processing temperature information.
Claim 10
Dependent Claim
67 words
Test circuitry formed on a semiconductor wafer, the test circuitry comprising: N test circuits (34) for providing signals through a compliant interconnect media and for monitoring voltage and current through the compliant interconnect media, the N test circuit being subdivided into M distinct groups; and M feedback circuits (36), each of the M feedback circuits monitoring temperature information from a unique one of the M distinct groups.
References Cited (Backward Citations)
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