Patent EP0696874A2 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0696874A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Dram mapping for a digital video data decompression processor

Assignee: Arris Technology Inc
•
Filing: 1995-07-31
•
Granted: —
•
Expires: 2015-07-31
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A random access memory (22) of a digital video decompression processor (20) is mapped to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream. A FIFO buffer (86) is provided in the RAM for the compressed video bitstream. A first luminance anchor frame buffer (70) and a first chrominance anchor frame buffer (74) are provided for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames. A second luminance anchor frame buffer (76) and second chrominance anchor frame buffer (78) are provided for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict the B-frames. A first B-frame luminance buffer (80) is provided in the RAM and sized to store less than 100% of the amount of luminance data in a first B-frame field. A second B-frame luminance buffer (82) is provided in the RAM and sized to store at least 100% of the amount of luminance data in a second B-frame field. A B-frame chrominance buffer (84) is provided in the RAM to store at least 100% of the amount of chrominance data in a B-frame. The anchor frames and B-frames are read from the RAM (22) to enable the reconstruction of successive video frames. The memory mapping is particularly well suited for the decompression of PAL formatted video in an MPEG-2 decoder.

Inventors

  • 👤 Chris Hoogenboom

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-07 19:43
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N19/426; H04N19/427; H04N19/60; H04N19/61

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 225 words
A digital video decompression processor for a compressed video bitstream representative of successive video frames of pixel data, comprising a memory manager for mapping a random access memory to provide: a FIFO buffer for said compressed video bitstream; a first luminance anchor frame buffer and a first chrominance anchor frame buffer for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames and for subsequent output for use in reconstructing said successive video frames; a second luminance anchor frame buffer and a second chrominance anchor frame buffer for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict said B-frames and for subsequent output for use in reconstructing said successive video frames; a first B-frame luminance buffer sized to store less than 100% of the amount of luminance data in a first B-frame field for use in reconstructing said successive video frames; a second B-frame luminance buffer sized to store at least 100% of the amount of luminance data in a second B-frame field for use in reconstructing said successive video frames; and a B-frame chrominance buffer sized to store at least 100% of the amount of chrominance data in a B-frame for use in reconstructing said successive video frames.
Claim 2
Dependent Claim 52 words
A digital video decompression processor in accordance with claim 1 wherein said FIFO buffer comprises substantially all of the storage space left in said random access memory after accounting for said first and second luminance and chrominance anchor frame buffers, said first and second B-frame luminance buffers and said B-frame chrominance buffer.
Claim 3
Dependent Claim 87 words
A digital video decompression processor in accordance with claim 1 or 2 for decompressing an MPEG-2 video signal using B-frames in a PAL format and having video frames containing 576 video lines of 704 pixels each, wherein said first and second luminance anchor frame buffers each accommodate 576 video lines, said first and second chrominance anchor frame buffers each accommodate 288 video lines, said first B-frame luminance buffer accommodates 184 video lines, and said second B-frame luminance buffer and B-frame chrominance buffer each accommodate 320 video lines.
Claim 4
Dependent Claim 23 words
A digital video decompression processor in accordance with any of the preceding claims, wherein said random access memory is a sixteen megabit memory.
Claim 5
Dependent Claim 44 words
A digital video decompression processor in accordance with any of the preceding claims, wherein said memory manager provides a portion of said random access memory equivalent to about one video line for storing frame specific data required to properly display a decoded video frame.
Claim 6
Dependent Claim 87 words
A digital video decompression processor in accordance with claim 1 or 2 for decompressing an MPEG-2 video signal using B-frames in a PAL format and having video frames containing 576 video lines of 352 pixels each, wherein said first and second luminance anchor frame buffers each accommodate 576 video lines, said first and second chrominance anchor frame buffers each accommodate 288 video lines, said first B-frame luminance buffer accommodates 144 video lines, and said second B-frame luminance buffer and B-frame chrominance buffer each accommodate 288 video lines.
Claim 7
Dependent Claim 20 words
A digital video decompression processor in accordance with claim 6 wherein said random access memory is an eight megabit memory.
Claim 8
Dependent Claim 41 words
A digital video decompression processor in accordance claim 6 or 7, wherein said memory manager provides a portion of said random access memory equivalent to about one video line for storing data required to properly order a video frame for display.
Claim 9
Dependent Claim 89 words
A digital video decompression processor in accordance with any of the preceding claims further comprising: means for decoding said compressed video bitstream to reconstruct said B-frames from predictions based on said anchor frames; wherein said memory manager: writes portions of a B-frame being reconstructed into corresponding portions of said B-frame buffers, and commences reading first field luminance data for the B-frame being reconstructed from said first B-frame luminance buffer, for use in reconstructing a video frame for display, before the B-frame has been entirely reconstructed by said decoding means.
Claim 10
Dependent Claim 40 words
A digital video decompression processor in accordance with any of the preceding claims wherein said first B-frame luminance buffer is sized to store only about 50% to 80% of the amount of luminance data contained in said first B-frame field.
Claim 11
Dependent Claim 37 words
A digital video decompression processor in accordance with claim 10 wherein said first B-frame luminance buffer is sized to store only about 50% to 66% of the amount of luminance data contained in said first B-frame field.
Claim 12
Dependent Claim 62 words
A digital video decompression processor in accordance with any of the preceding claims wherein: said second B-frame luminance buffer is sized to store about 100% to 120% of the amount of luminance data contained in said second B-frame field; and said B-frame chrominance buffer is sized to store about 100% to 120% of the amount of chrominance data contained in said B-frame.
Claim 13
Independent Claim 227 words
A method for mapping a random access memory (RAM) of a digital video decompression processor to enable the reconstruction of successive video frames of pixel data represented by a compressed video bitstream, comprising the steps of: providing a FIFO buffer in said RAM for said compressed video bitstream; providing a first luminance anchor frame buffer and a first chrominance anchor frame buffer in said RAM for storing a full frame of luminance data and a full frame of chrominance data for a first anchor frame used to predict B-frames; providing a second luminance anchor frame buffer and a second chrominance anchor frame buffer in said RAM for storing a full frame of luminance data and a full frame of chrominance data for a second anchor frame used to predict said B-frames; providing a first B-frame luminance buffer in said RAM sized to store less than 100% of the amount of luminance data in a first B-frame field; providing a second B-frame luminance buffer in said RAM sized to store at least 100% of the amount of luminance data in a second B-frame field; and providing a B-frame chrominance buffer in said RAM sized to store at least 100% of the amount of chrominance data in a B-frame; wherein said anchor frames and B-frames are read from said RAM to enable the reconstruction of said successive video frames.
Claim 14
Dependent Claim 57 words
A method in accordance with claim 13 wherein said step of providing said FIFO buffer allocates to the FIFO buffer substantially all of the storage space left in said random access memory after accounting for said first and second luminance and chrominance anchor frame buffers, said first and second B-frame luminance buffers and said B-frame chrominance buffer.
Claim 15
Dependent Claim 101 words
A method for storing and retrieving B-frame data from the RAM mapped in accordance with the method of claim 13 or 14, comprising the steps of: writing first and second field luminance and chrominance portions of a B-frame being reconstructed into corresponding portions of said B-frame buffers; and reading first field luminance data for the B-frame being reconstructed from said first B-frame luminance buffer before the B-frame has been entirely reconstructed; wherein storage locations of said first B-frame luminance buffer are available for reuse to provide storage space for remaining portions of said B-frame as the reconstruction of the B-frame continues.
Claim 16
Independent Claim 38 words
A method in accordance with one of claims 13 to 15 wherein said first B-frame luminance buffer is sized to store only about 50% to 80% of the amount of luminance data contained in said first B-frame field.
Claim 17
Dependent Claim 34 words
A method in accordance with claim 16 wherein said first B-frame luminance buffer is sized to store only about 50% to 66% of the amount of luminance data contained in said first B-frame field.
Claim 18
Independent Claim 60 words
A method in accordance with one of claims 13 to 17 wherein: said second B-frame luminance buffer is sized to store about 100% to 120% of the amount of luminance data contained in said second B-frame field; and said B-frame chrominance buffer is sized to store about 100% to 120% of the amount of chrominance data contained in said B-frame.

References Cited (Backward Citations)

US5091782A Cited
US5068724A Cited
US5093720A Cited
US5057916A Cited
US5235419A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag