Patent EP0681186A2 successfully refreshed from Google Patents.
EP0681186A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for probing a semiconductor wafer
Assignee: Motorola Solutions Inc
•
Filing: 1995-04-18
•
Granted: —
•
Expires: 2015-04-18
Abstract
Abstract A method for probing a semiconductor wafer utilizes an array probe assembly (60) which includes a production package substrate (64). Substrate (64) is used to transform a configuration of conductive pads (74) on a probe card (62) into a configuration which matches that of conductive bumps (54) on a semiconductor die (52). Array probe assembly (60) may also include an array probe head (68) having probe wires (84) for coupling conductive pads (80) on substrate (64) with conductive bumps (54) on die (52). After probing the die, the die are assembled into a final packaged semiconductor device (110) which includes a substrate (90) which is nearly identical to the substrate used in the array probe assembly. Use of a prodution package substrate in the array probe assembly reduces the cost of the array probe assembly, and results in more accurate testing since the substrate in the array probe assembly will emulate the performance of the die in the final packaged device.
Inventors
- 👤 Thomas F. Lum
- 👤 James F. Wenzel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 04:51
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07364; G01R1/07378; H; H10; H10P; H10P95/00; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W74/00; H10W74/10; H10W74/15; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
173 words
A method for probing wafers comprising the steps of: providing a semiconductor wafer (50) having a plurality of semiconductor die (52) formed thereon, each die having a plurality of conductive bumps (54) arranged in a first array; providing a probe card (62) having a plurality of conductive pads (74) arranged in a second array different from the first array; providing a first production package substrate (64) having a first side which has a plurality of conductive pads (80) arranged in the first array and an opposing second side which has a plurality of conductive pads (78) arranged in the second array, wherein the plurality of conductive pads of the second side of the substrate are electrically connected to the plurality of conductive pads on probe card; and probing a first die of the plurality of semiconductor die by electrically connecting the plurality of conductive pads on the first side of the first production package substrate with the plurality of conductive bumps on the first die and performing electrical tests on the first die.
Claim 2
Dependent Claim
84 words
The method of claim 1 further comprising the steps of: providing a second production package substrate (90) substantially identical to the first production package substrate, the second production package substrate having a first side which has a plurality of conductive pads (98) arranged in the first array and an opposing second side which has a plurality of conductive pads (94) arranged in the second array; separating the first die from the semiconductor wafer; and packaging the first die using the second production package substrate.
Claim 3
Independent Claim
236 words
A method for probing wafers comprising the steps of: providing a probe assembly (60) for use in a tester, the probe card assembly comprising: a probe card (62) having a plurality of conductive traces (70) which electrically terminate in a first array configuration; a first production package substrate (64) having first and second opposing sides, wherein the first side has a first plurality of conductive pads (78) arranged in the first array configuration, wherein the second side has a second plurality of conductive pads (80) electrically connected to the first plurality of pads and in a second array configuration which is smaller in area than the first array configuration, and wherein the first plurality of pads of the substrate is electrically connected to the plurality of conductive traces of the probe card; a probe needle assembly (68) having a plurality of probe needles (80) arranged in the second array configuration and electrically connected to the second plurality of pads on the second side of the substrate; providing a semiconductor wafer (50) having a plurality of semiconductor die (52), each die having a plurality of die pads (54) arranged in the second array configuration; probing a first semicondutor die of the plurality of semiconductor die by bringing the plurality of die pads of the first die into electrical contact with the plurality of probe needles and using the test to perform electrical diagnostics on the first die.
Claim 4
Dependent Claim
136 words
The method of claim 3 further comprising the steps of: singulating the first die from the wafer; providing a second production package substrate (90) which is substantially identical to the first production package substrate, the second substrate likewise having first and second opposing sides, wherein the first side has a first plurality of conductive pads (94) arranged in the first array configuration, wherein the second side has a second plurality of conductive pads (98) electrically connected to the first plurality of pads and in a second array configuration which is smaller in area than the first array configuration; mounting the first die on the second side of the production package substrate; and electrically connecting the plurality of die pads of the first die and the second plurality of conductive pads of the second production package substrate.
Claim 5
Dependent Claim
49 words
The method of claim 3 wherein the step of providing a probe assembly comprises providing a probe assembly having a probe needle assembly (68) having a plurality of probe needles (84), wherein the plurality of probe needles comprises a plurality of probe wires arranged in the second array configuration.
Claim 6
Independent Claim
238 words
A method for probing wafers comprising the steps of: providing a semiconductor wafer (50) having a plurality of semiconductor die (52) formed thereon, wherein each die has a plurality of die pad (54) arranged in a first configuration; providing a probe card assembly (60) for use in a tester, the probe card assembly comprising: a probe card (62) having a plurality of conductive traces (70) configured for suitable electrical connection to the tester, and having a plurality of conductive pads arranged in a second configuration (74), different from the first configuration, and electrically coupled to the plurality of conductive traces; a first production package substrate (64) having a first surface with a plurality conductive pads (78) arranged in the second configuration (the BGA array) and electrically connected to the plurality of conductive pads on the probe card, and having a second surface opposite the first surface, the second surface having a plurality of conductive pads (80) arranged in the first configuration; and means (68) for electrically connecting the plurality of conductive pads on the second surface of the first production package substrate with the plurality of conductive pads on a first die of the plurality of die; bringing the semiconductor wafer in proximity to the probe card assembly such that electrical connections are made between the plurality of conductive pads on the first die and the conductive traces on the probe card; and electrically testing the first die.
Claim 7
Dependent Claim
66 words
The method of claim 6 further comprising the steps of: singulating the first die from the wafer; providing a second production package (90) substantially identical to the first production package substrate; the second production package likewise having first and second surfaces; mounting the first die on the second surface of the production package substrate; and electrically conntecting the first die to the second production package substrate.
Claim 8
Dependent Claim
42 words
The method of claim 6 wherein the step of providing a probe card assembly comprises providing a probe card assembly wherein the means comprises a probe needle assembly (68) having a plurality of probe wires (84) substantially fixed in the first configuration.
Claim 9
Dependent Claim
34 words
The method of claim 3 or 6 wherein the step of providing a semiconductor wafer comprises providing a semiconductor wafer having a plurality of die pads, wherein each die pad comprises a conductive bump.
Claim 10
Dependent Claim
25 words
The method of claim 2, 4, or 7 wherein the first production package substrate and the second production package substrate each comprise a ceramic substrate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.