Self-aligned via using low permittivity dielectric

Claim 2

The method of claim 1, further comprising providing said organic-containing layer having a thickness between 50% and 150% the thickness of said patterned conductors, as measured in the gap between said conductors, said organic-containing layer having a dielectric constant of less than 3.5, whereby said organic-containing dielectric layer acts as an etch stop and prevents overetching due to mask misalignment or uneven device topography, and whereby the capacitance between adjacent pairs of said conductors is reduced as compared to a silicon dioxide dielectric.

Claim 3

The method of claim 1 or claim 2 , further comprising providing said layer of patterned conductors as an interconnection layer.

Claim 4

The method of claim 3 , further comprising selecting said interconnection layer is from the group consisting of: aluminum, copper, titanium, platinum, gold, tungsten, polysilicon, tantalum, TiN, TiSi₂, and combinations thereof.

Claim 9

The method of claim 8 , wherein said step of depositing an organic-containing material comprises spinning on an SOG containing 10% to 100% polymer by weight and annealing at a temperature of greater than 300 degrees C.

Claim 11

The method of claim 10, further comprising providing said inorganic dielectric layer composing more than 95% silicon dioxide, silicon nitride, or combinations thereof.

Claim 13

The method of claim 14 , further comprising providing said inorganic low-k sublayer composing a porous silicide.

Claim 14

The method of claim 12 or 13 , further comprising etching said vias through said organic-containing sublayer, with an second etchant which is selective to said inorganic sublayer, whereby said inorganic sublayer acts as an etch stop.

Claim 17

The method of claim 16 , further comprising conformally depositing said organic-containing dielectric layer over said patterned conductors and said substrate.

Claim 18

The method of claim 16 or 17 , further comprising forming conductors in said vias to provide electrical contacts to said polysilicon layer as well as to source-drain regions of said semiconductor device.

Claim 19

A semiconductor device which comprises: a layer of patterned conductors formed on a substrate; an organic-containing dielectric layer spanning at least some of the space between at least two of said patterned conductors; an inorganic dielectric layer covering said organic-containing dielectric layer and any exposed portions of said conductors; at least two vias formed through said inorganic dielectric layer by a process which selectively etches said inorganic dielectric without substantially etching said organic-containing dielectric; and at least two electrical connections formed by filling said vias with a conducting material, said electrical connections connecting said patterned conductors to a second level of patterned conductors deposited above said inorganic dielectric layer.

Claim 20

The device as in claim 20, wherein said organic-containing layer has a dielectric constant of less than 3.5; and has a thickness as measured in the gap between conductors of 50% to 150% the thickness of said patterned conductors.

Claim 21

A semiconductor device as in claim 19 or 20 , wherein said layer of patterned conductors is a polysilicon layer, said polysilicon layer also forming the top plate of gates on field effect transistors integrated into said semiconductor device, and wherein said organic-containing dielectric layer is deposited conformally over said patterned conductors and said substrate.

Claim 22

A semiconductor device as in claim 21 , wherein said vias are used to form contacts to said polysilicon layer as well as to source-drain regions of said semiconductor device.