Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
121 words
A method of steering instructions to a first integer arithmetic logic unit (36), a second integer arithmetic logic unit (37) and/or a floating point unit (35) in a computer system, comprising the steps of: (a) fetching instructions from a main memory; (b) predecoding the instructions to generate predecode bits which indicate whether and how the instructions may be bundled; (c) storing the instructions and the predecode bits in an instruction cache; (d) fetching the instructions from the instruction cache with the predecode bits; and (e) steering on the basis of the predecode bits each of the instructions to one of the first integer arithmetic logic unit, the second integer arithmetic logic unit (37) and the floating point unit (35) for execution.
Claim 2
Dependent Claim
23 words
A method as in claim 1, wherein in step (b) the predecode bits indicate whether two consecutive instructions may be bundled for execution.
Claim 3
Dependent Claim
28 words
A method as in claim 2, wherein in step (b) the predecode bits indicate whether two consecutive instructions which may be bundled for execution are non-aligned or aligned.
Claim 4
Independent Claim
51 words
A method as in any preceding claim, wherein in step (b) the predecode bits identify for each pair of bundled instructions to which of the first integer arithmetic logic unit (36), the second integer arithmetic logic unit (37) and the floating point unit (35) a particular instruction is to be steered.
Claim 5
Independent Claim
27 words
A method as in ny preceding claim, wherein in step (a) the instructions are fetched from the main memory two at a time in a double word.
Claim 6
Dependent Claim
193 words
A computer system comprising: a main memory (11); an instruction cache (13); and a processor (12) coupled to the main memory (11) and the instruction cache (13), the processor (12) including: memory interface means (26), coupled to the main memory (11), for fetching instructions from the main memory (11), predecoding means (40,41,43,44), coupled to the memory interface means (26), for predecoding the instructions to generate predecode bits, the predecode bits indicating whether and how the instructions may be bundled, interface means (24), coupled to the predecoding means (40,41,43,44) and the instruction cache (13), for storing the instructions and the predecode bits in the instruction cache (13) and for fetching the instructions from the instruction cache (13) with the predecode bits, a first arithmetic logic unit (36), a second arithmetic logic unit (37), and steering means (34,45), coupled to the interface means (24), the first arithmetic logic unit (36) and the second arithmetic logic unit (37), for steering each of the instructions to one of the first integer arithmetic logic unit (36) and the second integer arithmetic logic unit (37) for execution, the steering means (34,45) utilizing the predecode bits to steer the instructions.
Claim 7
Dependent Claim
52 words
A computer system as in claim 6, wherein the predecode bits generated by the predecoding means (40,41,43,44) are able to identify for each pair of bundled instructions to which of the first integer arithmetic logic unit (36) and the second integer arithmetic logic unit (37) a particular instruction is to be steered.
Claim 8
Dependent Claim
69 words
A computer system as in claim 6 or 7, wherein the predecoding means (40,41,43,44) includes: a first predecode register (40) for holding an even word instruction of an instruction pair curently being decoded; a second predecode register (41) for holding an odd word instruction of the instruction pair currently being decoded; and a third predecode register (43) for holding an odd word instruction of an instruction pair previously predecoded.
Claim 9
Dependent Claim
42 words
A computer system as in claim 6,7 or 8 wherein the steering means (34,35) includes a state machine (45), a current state of the state machine (45) determining which of the predecode bits the steering means (34,45) utilizes to steer the instructions.
Claim 10
Dependent Claim
45 words
A computer system as in any one of claims 6 to 9, wherein the processopr (12) includes a floating point unit (35) coupled to the steering means (34,45), the steering means (34,45) being operative to steer floating point instructions to the floating point unit (35).