Variable latency, output buffer and synchronizer for synchronous memory

Abstract

Abstract The present invention relates to an output buffer for driving an output driver of a random access memory (RAM) circuit to either of opposite binary data values from a data source and a clock wherein the relative timing of data and clock signals is variable or uncertain, comprised of a source of data signals having pulses one of which has a rising edge either being earlier than a leading edge of a data pulse, being later than the leading edge of the data pulse, or being in a race condition with the data pulse, a source of data signals, a latency counter for receiving the clock signals and for outputting a latent control, apparatus for summing the latent clock signal and the data pulse, and apparatus for providing a signal to an output driver from the summing apparatus which is in sync with the latent clock signal. The invention also relates to a variable latency output circuit for a synchronous dynamic random access memory (SDRAM) comprised of apparatus for reading a pair of complementary data bus lines, apparatus for receiving an output signal of the reading apparatus, an output buffer for receiving an output signal of the receiving apparatus, a latency counter for receiving and counting a clock signal and for providing an output enable signal upon counting a predetermined number of clock pulses based on a predetermined latency, and apparatus for enabling the reading apparatus, the receiving apparatus and the output buffer to pass data logic levels from the data bus lines to the output driver within one clock cycle in the event of a latency of one, for delaying the data logic levels for one clock cycle in the event of a latency of two, and for delaying the data logic levels for two clock cycles in the event of a latency of three.

Inventors

• 👤 Tomasz Wojcicki
• 👤 Graham Allan
• 👤 Francis Larochelle

Bibliographic Details