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EP0656628A2
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Programmed reference
Assignee: Advanced Micro Devices Inc
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Filing: 1994-11-10
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Granted: —
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Expires: 2014-11-10
Abstract
Abstract A programmable reference used to identify a state of an array cell in a multi-density or low voltage supply flash EEPROM memory array. The programmable reference includes one or more reference cells, each reference cell having a floating gate which is programmed to control its threshold value. The array cells are read by applying an identical voltage to the gate of the array cell and the reference cell and comparing outputs to determine the array cell state. During read of an array cell, the programmable reference cell is biased the same as the array cell, so that the difference in threshold values between reference cells and array cells remain constant with a change in V cc . Circuitry is included for programming the reference cells utilizing a simple resistor ratio. Programming is performed at test time, preferably by the manufacturer, to assure V cc remains within strict tolerances. The array cells are programmed and read without resistor biasing and under looser tolerances using the reference cells at a later time.
Inventors
- 👤 Shane C. Hollmer
- 👤 Lee E. Cleveland
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:01
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C11/00; G11C11/56; G11C11/5621; G11C11/5642; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G11C11/5628; G11C2211/00; G11C2211/56; G11C2211/563; G11C2211/5634
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
42 words
A reference for determining a state in a plurality of possible states stored by an array cell in a memory array, the reference comprising: a programmable reference cell having a floating gate which stores an electrical charge programmed to a predetermined level.
Claim 2
Dependent Claim
18 words
The reference of Claim 1 wherein the reference cell and the array cell are biased substantially the same.
Claim 3
Dependent Claim
36 words
The reference of Claim 1 wherein a select voltage applied to the gate of the array cell to determine the state stored by the array cell is also applied to the gate of the reference cell.
Claim 4
Dependent Claim
27 words
The reference of Claim 3 wherein when the select voltage is varied a working margin between the plurality of possible array cell states does not substantially vary.
Claim 5
Dependent Claim
40 words
The reference of Claim 1 wherein the reference cell and the array cell are included as core cells on a single integrated circuit so that the reference cell and the array cell have substantially the same rate of thermal expansion.
Claim 6
Dependent Claim
132 words
A memory comprising: an array cell having a gate, an output, and an array threshold value set to one of n array threshold values; n-1 programmable reference cells, each reference cell having a gate, an output and a floating gate which stores an electrical charge to allow a reference threshold value to be programmed, each respective reference cell having its reference threshold value programmed between two different successive ones of the n array threshold values; a selector for supplying a select voltage to the gate of the array cell and the gates of the reference cells; and a comparison means coupled to receive the array cell output and the reference cell outputs, the comparison means providing a signal indicating which of the n array threshold values is held by the array cell.
Claim 7
Dependent Claim
19 words
The memory of Claim 6 wherein the programmable reference cells and the array cell are biased substantially the same.
Claim 8
Dependent Claim
35 words
The memory of Claim 6 wherein the select voltage applied to the gate of the array cell has substantially the same value as the select voltage applied to the gate of the programmable reference cells.
Claim 9
Dependent Claim
42 words
The memory of Claim 6 wherein the programmable reference cells and the array cell are included as core cells on a single integrated circuit so that the programmable reference cells and the array cell have substantially the same rate of thermal expansion.
Claim 10
Dependent Claim
30 words
The memory of Claim 6 wherein when a value of the select voltage is varied, a working margin between the array cell output and the reference cell outputs remains constant.
Claim 11
Dependent Claim
284 words
A memory comprising: an array cell having a gate and a floating gate which stores an electrical charge to allow an array threshold value to be programmed; n program reference cells, each program reference cell having a gate and a floating gate which stores an electrical charge to allow a program reference threshold value to be programmed; n-1 read reference cells, each read reference cell having a gate and a floating gate which stores an electrical charge to allow a read reference threshold value to be programmed; a reference program-verify means for alternately applying program and reference verify voltages to the n program reference cells to program the n program reference cells to different n program reference threshold values and for alternately applying the program and reference verify voltages to the n-1 read reference cells to program the read reference threshold value for each successive read reference cell between two successive ones of the program reference threshold values; an array program-verify means for alternately applying program and array verify voltages to the floating gate of the array cell until the array threshold value is programmed to be equal to the program reference threshold value of a given one of the n program reference cells; a selector for supplying a select voltage to the gate of the array cell and the gates of the read reference cells to obtain an array cell output and a read reference cell output from each of the read reference cells; and a comparison means coupled to receive the array cell output and the read reference cell outputs, the comparison means providing a signal indicating the given one of the n program reference cells used to program the array cell.
Claim 12
Dependent Claim
22 words
The memory of Claim 11 wherein the reference verify voltage has a value which varies significantly less than the array verify voltage.
Claim 13
Dependent Claim
32 words
The memory of Claim 11 wherein when the array cell is being read or programmed, the read reference cells, the program reference cells and the array cell are biased substantially the same.
Claim 14
Dependent Claim
35 words
The memory of Claim 11 wherein the select voltage applied to the gate of the array cell has substantially the same value as the select voltage applied to the gate of the read reference cells.
Claim 15
Dependent Claim
50 words
The memory of Claim 11 wherein the program reference cells, the read reference cells and the array cell are included as core cells on a single integrated circuit so that the program reference cells, the read reference cells and the array cell have substantially the same rate of thermal expansion.
Claim 16
Dependent Claim
37 words
The memory of Claim 11 wherein when a value of the select voltage is varied a working margin between outputs of the program reference cells, the read reference cell outputs and the array cell output remains constant.
Claim 17
Independent Claim
337 words
An apparatus for programming a plurality of reference cells used to read a threshold voltage of an array cell, each reference cell in the plurality of reference cells having a REFWL connection at its gate and a REFBL connection at its drain, the apparatus comprising: a reference count circuit for sequentially selecting a particular reference cell in the plurality of reference cells, the reference count circuit indicating the particular reference cell being selected by outputting a COL signal and a ROW signal and sequencing to a next sequential reference cell when a RDSO signal is received; a program-verify signal circuit for supplying a program-verify voltage for applying to the gate of the particular reference cell to alternately program the particular reference cell and verify if the particular reference cell is fully programmed, and for supplying a program voltage for applying to the drain of the particular reference cell during programming, and for supplying a verify signal during verification; a sense bias circuit for receiving the ROW signal and the program-verify voltage and coupling the program-verify voltage to the REFWL connection of the particular reference cell as controlled by the ROW signal; a data buffer reference circuit for receiving the COL signal and the program voltage and coupling the program voltage to the REFBL connection of the particular reference cell as controlled by the COL signal; a golden bit cell having a MSTRWL connection at its gate and a GOLBL connection at its drain; a reference bias circuit having a plurality of resistance ratios, each resistance ratio being coupled between a read voltage and the MSTRWL connection as controlled by the COL signal; and a comparison circuit for receiving the COL signal, the verify signal, a GOLBL signal from the GOLBL connection and a REFBL signal from the REFBL connection of the particular reference cell, and comparing the GOLBL signal to the REFBL signal during application of the verify signal and outputting the RDSO signal when the GOLBL signal is substantially equal to voltage of the REFBL signal.
Claim 18
Dependent Claim
23 words
The apparatus of Claim 17 wherein the plurality of reference cells are also utilized to program a threshold voltage of an array cell.
Claim 19
Dependent Claim
120 words
The apparatus of Claim 17 wherein the comparison circuit comprises: a reference sense circuit for receiving the COL signal and the verify signal and outputting a REFSEN signal indicative of the COL signal when the verify signal is applied; a first preamplifier receiving the REFSEN signal, and the REFBL signal and outputting a SAREF voltage indicative of the REFBL signal when the REFSEN signal is applied; a second preamplifier receiving the REFSEN signal, and the GOLBL signal and outputting a SAREFGB voltage indicative of the GOLBL signal when the REFSEN signal is applied; a sense amplifier receiving the SAREF voltage and the SAREFGB voltage and outputting the RDSO signal when the SAREF voltage and the SAREFGB voltage are substantially equal.
Claim 20
Independent Claim
198 words
A method of programming n reference cells comprising the successive steps of: (a) selecting a first of the n reference cells as a selected reference cell and a first of n resistor ratios as a selected resistor ratio; (b) coupling the selected resistor ratio to a gate of a golden bit cell; (c) applying a program voltage to increase charge stored on a floating gate of the selected reference cell; (d) applying a reference verify voltage to the gate of the selected reference cell and through the selected resistor ratio to the gate of the golden bit to create a selected reference cell output and a golden bit cell output; (e) comparing the selected reference cell output and the golden bit cell output and proceeding to step (c) if the selected reference cell output is not substantially equal to the golden bit cell output; (f) selecting a next successive reference cell in the n reference cells as the selected reference cell and a next successive resistor ratio in the n resistor ratios as the selected resistor ratio and proceeding to step (b) if the n th reference cell in the n reference cells has not been previously selected.
Claim 21
Independent Claim
121 words
A method of programming an array cell comprising the steps of: (a) selecting a reference cell in a plurality of reference cells having a floating gate storing a charge representative of a value to which the array cell is to be programmed; (b) applying a program voltage to increase charge stored on a floating gate of the array cell; (c) applying an array verify voltage to a gate of a reference cell and a gate of the array cell to create a reference cell output and an array cell output; and (d) comparing the reference cell output and the array cell output and proceeding to step (b) if the array cell output is not substantially equal to the reference cell output.
Claim 22
Dependent Claim
18 words
The method of Claim 21 wherein the reference cell is programmed according to the method of Claim 20.
Claim 23
Dependent Claim
22 words
The method of Claim 22 wherein the reference verify voltage has a value which varies significantly less than the array verify voltage.
Claim 24
Independent Claim
126 words
A method of reading an array cell which stores one of n array threshold values comprising the steps of: applying a read voltage to a gate of an array cell to generate an array cell output; applying the read voltage to gates of a plurality of reference cells to generate respective reference cell outputs, each reference cell having a floating gate for storing a different electrical charge to allow a reference threshold value to be programmed, each successive reference cell having its reference threshold value programmed between two different successive ones of the n array threshold values; and comparing the array cell output and the reference cell outputs and providing a signal indicating which of the n array threshold values is held by the array cell.
Claim 25
Dependent Claim
35 words
The programmable reference of Claim 1 wherein the read voltage applied to the gate of the array cell has substantially the same value as the select voltage applied to the gates of the reference cells.
References Cited (Backward Citations)
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