Patent EP0656579A2 successfully refreshed from Google Patents.
EP0656579A2
Expired / Lapsed
EP
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Power management for computer system
Assignee: Advanced Micro Devices Inc
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Filing: 1994-11-23
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Granted: —
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Expires: 2014-11-23
Abstract
Abstract A system oscillator gating technique is provided for a power management unit of a computer system for controlling the application of power to a system oscillator. An output signal from the power management unit is provided to turn off the external system oscillator when the computer system is in a power-conserving suspend state and to turn on the external system oscillator on when the computer system resumes to a ready state. Counters are provided to control the latency of the output signal when the power management unit enters and exits the suspend state. This latency provides time for the microprocessor clock and/or other clock signals associated with the system oscillator to shut off prior to the oscillator shutdown and provides time for the oscillator to stabilize prior to the restarting of the clock signal. As a result, power consumption of the computer system may be reduced while proper clock generation for the computer system is maintained.
Inventors
- 👤 Rita O'brien
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:00
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
148 words
A computer system comprising: an oscillator for generating a reference timing signal; a clock generator coupled to said oscillator and capable of generating a clock signal; a system monitor for monitoring a circuit portion of said computer system and capable of generating a suspend state signal indicative of whether said circuit portion is inactive; a clock control unit coupled to said clock generator and to said system monitor, wherein said clock control unit is capable of stopping said clock signal in response to an assertion of said suspend state signal and is capable of restarting said clock signal in response to a deassertion of said suspend state signal; and an oscillator power control unit coupled to said oscillator and to said system monitor, wherein said oscillator power control unit is capable of removing power supplied to said oscillator in response to an assertion of said suspend state signal.
Claim 2
Dependent Claim
21 words
The computer system as recited in Claim 1 further comprising a microprocessor, wherein said clock signal is provided to said microprocessor.
Claim 3
Dependent Claim
44 words
The computer system as recited in Claim 1 wherein said clock control unit generates a clock suspend signal that is provided to said clock generator, and wherein said clock generator stops said clock signal in response to an assertion of said clock suspend signal.
Claim 4
Dependent Claim
29 words
The computer system as recited in Claim 3 wherein said clock control unit asserts said clock suspend signal a predetermined time after said assertion of said suspend state signal.
Claim 5
Dependent Claim
23 words
The computer system as recited in Claim 4 further comprising a counter coupled to said clock control unit for controlling said predetermined time.
Claim 6
Dependent Claim
31 words
The computer system as recited in Claim 1 wherein said oscillator power control unit removes power supplied to said oscillator a predetermined time after said assertion of said suspend state signal.
Claim 7
Dependent Claim
24 words
The computer system as recited in Claim 6 further comprising a counter coupled to said oscillator power control unit for controlling said predetermined time.
Claim 8
Dependent Claim
29 words
The computer system as recited in Claim 1 wherein said clock control unit deasserts said clock suspend signal a predetermined time after a deassertion of said suspend state signal.
Claim 9
Dependent Claim
124 words
A power management unit connectable to a computer system including an oscillator for providing a timing reference signal, said power management unit comprising: a system monitor for monitoring a circuit portion of said computer system and capable of generating a suspend state signal indicative of whether said circuit portion is inactive; a clock control unit coupled to said system monitor, wherein said clock control unit is capable of generating a clock suspend signal in response to an assertion of said suspend state signal; and an oscillator power control unit coupled to said system monitor, wherein said oscillator power control unit is capable of generating an oscillator gating signal for controlling the application of power to said oscillator in response to said suspend state signal.
Claim 10
Dependent Claim
36 words
The power management unit as recited in Claim 9 wherein said clock suspend signal is provided to an output terminal of said power management unit for controlling the starting and the stopping of a clock signal.
Claim 11
Dependent Claim
30 words
The power management unit as recited in Claim 9 wherein said clock control unit asserts said clock suspend signal a predetermined time after said assertion of said suspend state signal.
Claim 12
Dependent Claim
23 words
The computer system as recited in Claim 11 further comprising a counter coupled to said clock control unit for controlling said predetermined time.
Claim 13
Dependent Claim
36 words
The computer system as recited in Claim 9 wherein said oscillator power control unit asserts said oscillator gating signal for removing power from said oscillator a predetermined time after said assertion of said suspend state signal.
Claim 14
Dependent Claim
25 words
The power management unit as recited in Claim 13 further comprising a counter coupled to said oscillator power control unit for controlling said predetermined time.
Claim 15
Dependent Claim
30 words
The power management unit as recited in Claim 9 wherein said clock control unit deasserts said clock suspend signal a predetermined time after a deassertion of said suspend state signal.
Claim 16
Dependent Claim
24 words
The power management unit as recited in Claim 15 further comprising a counter coupled to said clock control unit for controlling said predetermined time.
Claim 17
Dependent Claim
70 words
A power management method for removing and applying power to a system oscillator within a computer system comprising the steps of: monitoring a circuit portion of said computer system; entering a suspend state if said circuit portion is inactive; stopping a clock signal in response to said step of entering said suspend state; and removing power from said system oscillator in response to said step of entering said suspend state.
Claim 18
Dependent Claim
37 words
The power management method as recited in Claim 17 comprising the further step of waiting a predetermined time after said step of stopping said clock signal before performing said step of removing power from said system oscillator.
Claim 19
Dependent Claim
55 words
The power management method as recited in Claim 18 comprising the further steps of: entering a ready state when said circuit portion becomes active; reapplying power to said system oscillator in response to said step of entering said ready state; and restarting said clock signal in response to said step of entering said ready state.
Claim 20
Dependent Claim
32 words
The power management method as recited in Claim 19 wherein said step of restarting said clock signal is performed a predetermined time after said step of reapplying power to said system oscillator.
References Cited (Backward Citations)
No citation records indexed.
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