Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein

Claim 2

The delay-locked-loop based clock synthesizer of claim 1, further comprising a frequency divider for generating a modified reference signal from said reference signal, wherein a frequency of said modified reference signal is equal to a frequency of said reference signal divided by a predetermined value, said divider being connected to said first one of said delay elements such that said controllable delay circuit delays said modified reference signal by said adjustable amount of time to thereby generate said delayed reference signal.

Claim 3

The delay-locked-loop based clock synthesizer of claim 1, further comprising an inverter for inverting said reference signal, an output of said inverter being connected to said phase detector such that said phase detector generates a control signal indicative of a difference between a phase of said inverted reference signal and a phase of said delayed reference signal.

Claim 4

The delay-locked-loop based clock synthesizer of claim 1, wherein each of said delay elements delays said reference signal by a quantum of time given by: 1/(2*F*X) where F is the frequency of said reference signal and X is the number of delay elements in said controllable delay circuit.

Claim 5

The delay-locked-loop based clock synthesizer of claim 1, wherein each of said delay elements delays said reference signal by a quantum of time given by: 1/(F*X) where F is the frequency of said reference signal and X is the number of delay elements in said controllable delay circuit.

Claim 6

A delay-locked-loop based clock synthesizer for generating, from a reference signal, a clock signal having a frequency different from a frequency of the reference signal, comprising: a delay-locked-loop circuit, comprising a controllable delay circuit comprising a plurality of controllable delay elements serially connected to one another, each of said delay elements delaying said reference signal by an adjustable quantum of time such that said delay elements generate a plurality of delayed signals offset in time from one another and from said reference signal, a first multiplexer, coupled to one or more of said delay elements, for receiving the delayed signals generated by said one or more of said delay elements, and for routing one of said received delayed signals to an output of said first multiplexer, a phase detector, connected to said output of said first multiplexer, for receiving said routed delayed signal and said reference signal, and for generating a control signal indicative of a difference between a phase of said routed delayed signal and a phase of said reference signal, and feedback means, connected to said delay elements and said phase detector, for transferring said control signal from said phase detector to said delay elements, wherein each of said delay elements adjusts, in accordance with said control signal, said quantum of time by which they each delay said reference signal, such that said phase of said reference signal is synchronized with said phase of said routed delayed signal; one or more mixing circuits, each of said mixing circuits connected to said controllable delay circuit and associated with one of said one or more delay elements, said mixing circuits comprising combinational networks for logically combining said delayed signals such that said mixing circuits generate logically combined signals; and a second multiplexer, connected to said mixing circuits, for receiving said logically combined signals and for routing one of said logically combined signals to an output of said second multiplexer, wherein said routed logically combined signal represents said clock signal.

Claim 7

The delay-locked-loop based clock synthesizer of claim 6, wherein said first and second multiplexers receive and operate in accordance with a control signal which identifies one of said one or more of said delay elements such that said first multiplexer routes to said first multiplexer output the delayed signal generated by the delay element identified by the control signal, and said second multiplexer routes to said second multiplexer output the logically combined signal generated by the mixing circuit associated with the identified delay element.

Claim 8

The delay-locked-loop based clock synthesizer of claim 6, further comprising a divider for generating a modified reference signal from said reference signal, wherein a frequency of said modified reference signal is equal to a frequency of said reference signal divided by a predetermined value, said divider being connected to said controllable delay circuit such that said delay elements delay said modified reference signal to thereby generate said plurality of delayed signals.

Claim 9

The delay-locked-loop based clock synthesizer of claim 6, further comprising an inverter for inverting said reference signal, an output of said inverter being connected to said phase detector such that said phase detector generates a control signal indicative of a difference between a phase of said inverted reference signal and a phase of said routed delayed signal.

Claim 10

The delay-locked-loop based clock synthesizer of claim 6, wherein each of said delay elements delays said reference signal by a quantum of time given by: 1/(2*F*X) where F is the frequency of said reference signal and X is the number of delay elements electrically connected to said phase detector via said first multiplexer.