EP0654818A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device with solder bump and process for manufacturing the same
Assignee: Citizen Watch Co Ltd
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Filing: 1994-09-07
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Granted: —
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Expires: 2014-09-07
Abstract
Abstract A semiconductor device with solder bumps having a resin substrate of which both the upper and lower sides are laminated by a copper foil (3), which is provided with connection electrodes (6) for IC chips on the upper side and pad electrodes (7) for external connection on the lower side, joined with each other via through-holes (2), said pad electrodes (7) are provided with solder bumps (12), characterized by comprising forming a gold plated layer (18) on said connection electrode (6) and forming a plated layer (15) of a metal having affinity with solder, such as copper or nickel, on said pad electrodes (7).
Inventors
- 👤 Seiichi Citizen Watch Co. Ltd. Mimura
- 👤 Katsuji Citizen Watch Co. Ltd. Komatsu
- 👤 Yoshio Citizen Watch Co. Ltd. Iinuma
- 👤 Kazuhiko Citizen Watch Co. Ltd. Terashima
- 👤 Taichi Citizen Watch Co. Ltd. Miyazaki
- 👤 Shingo Citizen Watch Co. Ltd. Ichikawa
- 👤 Hiroyuki Citizen Watch Co. Ltd. Kaneko
- 👤 Junichiro Citizen Watch Co. Ltd. Shimizu
- 👤 Ienobu Citizen Watch Co. Ltd. Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 18:59
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/22; H05K3/24; H05K3/243; H05K3/40; H05K3/42; H05K3/425; H05K3/427; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W90/701; H05K2201/00; H05K2201/03; H05K2201/0332; H05K2201/0388; H05K2201/0391; H05K2201/10; H05K2201/10613; H05K2201/10621; H05K2201/10734; H05K2201/10954; H05K2201/10984; H05K2203/00; H05K2203/04; H05K2203/049; H05K2203/05; H05K2203/0562; H05K2203/0574; H05K2203/13; H05K2203/1377; H05K2203/1394; H05K3/30; H05K3/32; H05K3/34; H05K3/3465; H10W72/00; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
87 words
A semiconductor device with solder bumps having a resin substrate of which both the upper and lower sides are laminated by a copper foil, which is provided with connection electrodes for IC chips on the upper side and pad electrodes for external connection on the lower side, joined with each other via through-holes, said pad electrodes are provided with solder bumps, characterized by forming a gold plated layer on said connection electrodes and a plated layer of a metal having affinity with solder on said pad electrodes.
Claim 2
Dependent Claim
44 words
The semiconductor device with solder bumps as claimed in claim 1, wherein said gold plated layer on said connection electrodes is a multi-plated-layer of gold containing a bed plated layer and said metal plated layer on the pad electrodes is the bed plated layer.
Claim 3
Dependent Claim
26 words
The semiconductor device with solder bumps as claimed in claim 2, wherein said bed plated layer formed on the pad electrodes is a copper plated layer.
Claim 4
Dependent Claim
38 words
The semiconductor device with solder bumps as claimed in claim 2, wherein said bed plated layer formed on the pad electrodes consists of a copper plated layer and a nickel plated layer formed on the copper plated layer.
Claim 5
Dependent Claim
49 words
The semiconductor device with solder bumps as claimed in claim 2, wherein said bed plated layer formed on the pad electrodes consists of a copper plated layer and a nickel plated layer, and a flash gold plated layer formed on the copper plated layer and the nickel plated layer.
Claim 6
Dependent Claim
37 words
The semiconductor device with solder bumps as claimed in any of the above claims, wherein said metal plated layer formed on the pad electrodes is a plated layer of a metal selected from copper, nickel, and silver.
Claim 7
Dependent Claim
44 words
The semiconductor device with solder bumps as claimed in any of the above claims, further providing an anti-oxidation film on said plated layer of a metal having affinity with solder on said pad electrodes, to prevent oxidation of said metal having affinity with solder.
Claim 8
Dependent Claim
20 words
The semiconductor device with solder bumps as claimed in claim 7, wherein said anti-oxidation film is a hard oil film.
Claim 9
Dependent Claim
21 words
The semiconductor device with solder bumps as claimed in claim 7, wherein said anti-oxidation film is a thin gold plated layer.
Claim 10
Dependent Claim
36 words
The semiconductor device with solder bumps as claimed in claim 9, wherein said thin gold plated layer for preventing oxidation has a thickness smaller than the thickness of said gold plated layer on said connection electrodes.
Claim 11
Dependent Claim
27 words
The semiconductor device with solder bumps as claimed in claim 10, wherein the thickness of said gold plated layer for preventing oxidation is 0.1 µm or less.
Claim 12
Dependent Claim
203 words
A process for manufacturing a semiconductor device with solder bumps having a resin substrate of which both the upper and lower sides are laminated by a copper foil, which is provided with connection electrodes for IC chips on the upper side and pad electrodes for external connection on the lower side, joined with each other via through-holes, said pad electrodes are provided with solder bumps, characterized by comprising, a patterning step comprising forming connection electrodes for IC chips on the upper side of said resin substrate and forming pad electrodes on the lower side of said resin substrate, a resist step comprising forming open spaces of a resist pattern on said connection electrodes and pad electrodes, a first plating step comprising forming a part or whole of a bed plated layer on electrodes exposed in said open spaces of said resist pattern, a resist masking step comprising forming a mask on said pad electrodes on the lower side of the resin substrate for preventing formation of a gold plated layer, and a second plating step comprising forming a remaining bed plated layer and a gold plated layer or, solely, a gold plated layer, on said bed plated layer formed on said connection electrodes.
Claim 13
Dependent Claim
59 words
The process for manufacturing a semiconductor device with solder bumps as claimed in claim 12, wherein said bed plated layer in said first plating step is a copper plated layer, and the metal plating in said second plating step comprises forming a multi-plated layer of a nickel plated layer, a flash gold plated layer, and a gold plated layer.
Claim 14
Dependent Claim
67 words
The process for manufacturing a semiconductor device with solder bumps as claimed in claim 12, wherein plating of said bed plated layer in said first plating step comprises forming a multi-plated layer consisting of a copper plated layer and a nickel plated layer, and plating of said second plating step comprises forming a multi-plated layer consisting of a flash gold plated layer and a gold plated layer.
Claim 15
Dependent Claim
61 words
The process for manufacturing a semiconductor device with solder bumps as claimed in claim 12, wherein plating of said bed plated layer in said first plating step comprises forming a multi-plated layer consisting of a copper plated layer, a nickel plated layer, and a flash gold plated layer, and plating of said second plating step comprises forming a gold plated layer.
Claim 16
Dependent Claim
122 words
A process for manufacturing a semiconductor device with solder bumps according to claim 12, wherein the first plating step comprises forming a copper plated layer on electrodes exposed in said open spaces of said resist pattern, and the second plating step comprises forming a nickel plated layer, a flash gold plated layer, and a gold plated layer on said copper plated layer formed on said connection electrodes, and further including a step for removing said resist mask from the lower side of said resin substrate, a resist masking step comprising forming a resist mask on the upper side of said resin substrate, and a step for forming a silver plated layer on said pad electrodes on lower side of said resin substrate.
Claim 17
Dependent Claim
105 words
A process for manufacturing a semiconductor device with solder bumps according to claim 12, wherein the first plating step comprises forming a copper plated layer on electrodes exposed in said open spaces of said resist pattern, and the second plating step comprising forming a nickel plated layer, a flash gold plated layer, and a gold plated layer on said copper plated layer formed on said connection electrodes, and further including a step for removing said resist mask from the lower side of said resin substrate, and a step for forming an anti-oxidation film on said pad electrodes on the lower side of said resin substrate.
References Cited (Backward Citations)
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