Store "UNDO" for cache store error recovery

Claim 1

A central processing unit comprising: A) first basic processing unit means for executing computer instructions and producing a result for each computer instruction executed; B) second basic processing unit means for executing computer instructions and producing a result for each computer instruction executed; said first and second basic processing unit means concurrently executing the same computer instruction and producing the result of the execution of the same computer instruction concurrently; C) a cache unit, said cache unit including random access memory means for providing data concurrently to said first and second basic processing unit means for processing and for storing one of the two concurrently produced results produced by said basic processing unit means after execution of the same computer instruction by said first and second basic processing unit means using the data obtained from said random access memory; D) first result bus means for transmitting the result of the execution of each computer instruction by said first basic processing unit means to said cache unit; E) second result bus means for transmitting the result of the execution of each computer instruction by said second basic processing unit means to said cache unit; said first and second result bus means transmitting the results of the execution of the same computer instruction by said first and second basic processing unit means to said cache unit concurrently; F) said cache unit further including: 1) first buffer means for temporarily storing the data provided to said first and second basic processing unit means for processing; 2) comparing means for comparing the results transmitted to said cache unit by said first and second result bus means and for issuing an error signal if the results do not compare; 3) second buffer means for temporarily storing the result of the concurrent execution of the same instruction by one of said first and second basic processing unit means transmitted to said cache unit by said first and second result bus means; 4) merge means for performing a first merge operation to modify the data temporarily stored in said first buffer means by the results temporarily stored in said second buffer means; 5) third buffer means for temporarily storing at least a segment of the data provided to said first and second basic processing unit means for processing, which segment includes the portion of the data temporarily stored in said first buffer means which is subsequently modified during the first merge operation; and 6) control means responsive to the issuance of an error signal by said comparing means for directing said merge means to perform a second merge operation to further modify the once-modified contents temporarily stored in said first buffer means by merging the once-modified contents thereof with the contents of said third buffer means, thereby restoring the contents of said first buffer means to the same data last provided to said first and second basic processing unit means.