Efficient error detection in a VLSI central processing unit

Claim 1

A central processing unit of a data processing system comprising: A) a first basic processing unit including: 1) a first address and execution unit; 2) a first decimal numeric unit; 3) a first floating point unit; and 4) first intercommunication means coupling said first address and execution unit, said first decimal numeric unit and said first floating point unit to perform data manipulation operations within said first basic processing unit; B) a second basic processing unit including: 1) a second address and execution unit; 2) a second decimal numeric unit; 3) a second floating point unit; and 4) second intercommunication means coupling said first address and execution unit, said first decimal numeric unit and said first floating point unit to perform data manipulation operations within said second basic processing unit; C) a cache unit; D) a first result bus for coupling the results of data manipulation operations performed by said first basic processing unit to said cache unit for temporary storage; E) a second result bus for coupling the results of data manipulation operations performed by said second basic processing unit to said cache unit for temporary storage; F) comparison means within said cache unit for comparing the information received from said first result bus with the information received from said second result bus; and G) error reporting means within said cache unit to issue an error signal if a no-compare condition is sensed by said comparison means.