Patent EP0644475A2 successfully refreshed from Google Patents.
EP0644475A2
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EP
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Apparatus and method for controlling a peripheral bus clock signal
Assignee: Advanced Micro Devices Inc
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Filing: 1994-09-12
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Granted: —
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Expires: 2014-09-12
Abstract
Abstract A system accommodates a power conservation technique wherein a peripheral bus clock signal may be stopped (or slowed) in response to, for example, a power management unit. Prior to stopping the peripheral bus clock signal, an indicator signal is generated at a clock request line by a clock control circuit. If a slave device continues to require the peripheral bus clock signal, the slave device responsively generates a clock request signal. The clock control circuit receives the clock request signal and accordingly prevents the peripheral bus clock signal from stopping. If an alternate bus master requires mastership of the peripheral bus when the peripheral bus clock signal is stopped, the alternate bus master may be configured to assert a clock request signal for re-starting the peripheral bus clock. The clock request signal is broadcasted on the peripheral bus and is accordingly received by a clock control circuit. The clock control circuit responsively causes the re-starting of the peripheral bus clock signal. Subsequently, the alternate bus master can generate a bus request signal that is synchronous to the peripheral bus clock signal to thereby obtain a grant signal from a bus arbiter unit. The system may further be configured to achieve backwards compatibility with conventional alternate bus masters that are incapable of internally generating a bus request signal.
Inventors
- 👤 Douglas D. Gephardt
- 👤 Kelly M. Horton
- 👤 James R. Macdonald
- 👤 Rita O'brien
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:06
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3234; G06F1/324; G06F1/325; G06F1/3253; G06F13/00; G06F13/14; G06F13/36; G06F13/362; G06F13/364; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
144 words
A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface and arbiter unit coupled to said local bus and to said peripheral bus for orchestrating the transfer of data and address signals between said local bus and said peripheral bus and for arbitrating mastership of said peripheral bus; a clock generator circuit for providing a peripheral bus clock signal on said peripheral bus, wherein said peripheral bus clock signal is capable of being selectively stopped and re-started; an alternate bus master coupled to said peripheral bus wherein said alternate bus master is capable of asserting a clock request signal when said peripheral bus clock signal is stopped; and a clock control circuit coupled to said alternate bus master for re-starting said peripheral bus clock signal in response to the assertion of said clock request signal.
Claim 2
Dependent Claim
45 words
The computer system as recited in Claim 1 further comprising a latching circuit coupled to receive said clock request signal, wherein said latching circuit provides a synchronous bus request signal to said bus interface and arbiter unit in response to the peripheral bus clock signal.
Claim 3
Dependent Claim
68 words
The computer system as recited in Claim 1 wherein said alternate bus master includes a state machine that asserts said clock request signal when said peripheral bus clock signal is stopped and that asserts a synchronous bus request after said peripheral bus clock signal is re-started, wherein said synchronous bus request signal is provided to said bus interface and arbiter unit for requesting mastership of said peripheral bus.
Claim 4
Dependent Claim
16 words
The computer system as recited in Claim 1 wherein said peripheral bus is a PCI bus.
Claim 5
Dependent Claim
71 words
The computer system as recited in Claim 3 further comprising a power management unit coupled to said clock control circuit and to said clock generator circuit, wherein said power management unit provides a control signal to said clock generator for selectively stopping and re-starting said peripheral bus clock signal, and wherein said clock control circuit provides a command signal to said power management unit in response to said clock request signal.
Claim 6
Dependent Claim
36 words
The computer system as recited in Claim 5 wherein said power management unit stops said peripheral bus clock signal upon the occurrence of a predetermined condition after said microprocessor has attained mastership of said peripheral bus.
Claim 7
Dependent Claim
28 words
The computer system as recited in Claim 3 wherein said bus interface and arbiter unit asserts a bus grant signal in response to said synchronous bus request signal.
Claim 8
Dependent Claim
32 words
The computer system as recited in Claim 3 wherein said peripheral bus includes a control line for coupling said clock request signal from said alternate bus master to said clock control circuit.
Claim 9
Independent Claim
163 words
A system for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus comprising: a clock generator for generating said peripheral clock signal; a power management unit coupled to said clock generator for stopping said peripheral bus clock signal upon the occurrence of a predetermined condition; a clock control circuit coupled to receive an asynchronous clock request signal generated by an alternate bus master when said peripheral bus clock signal is stopped, wherein said clock control circuit generates a command signal in response to said asynchronous clock request signal that causes said power management unit to re-start said peripheral bus clock signal; and a bus arbiter unit responsive to a bus request signal generated by said alternate bus master, wherein said bus request signal is synchronous to said peripheral bus clock signal, and wherein said bus arbiter unit generates a grant signal in response to said bus request signal for indicating mastership of said peripheral bus to said alternate bus.
Claim 10
Dependent Claim
59 words
The system for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 9 wherein said alternate bus master includes a state machine that asserts said asynchronous clock signal when said peripheral bus clock signal is stopped and that asserts a synchronous request signal after said peripheral bus clock signal is re-started.
Claim 11
Dependent Claim
42 words
The system for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 9 wherein said clock control circuit includes a state machine that asserts said command signal in response to said asynchronous clock signal.
Claim 12
Dependent Claim
30 words
The system for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 9 wherein said peripheral bus is a PCI standard bus.
Claim 13
Dependent Claim
48 words
The system for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 9 further comprising a control line incorporated on said peripheral bus for coupling said asynchronous clock request signal from said alternate bus master to said clock control circuit.
Claim 14
Independent Claim
93 words
A method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus comprising the steps of: stopping said peripheral bus clock signal upon the occurrence of a predetermined condition; generating an asynchronous clock request signal within an alternate bus master; re-starting said peripheral bus clock signal in response to said asynchronous clock request signal; and generating a synchronous bus request signal within said alternate bus master after said peripheral bus clock signal has been re-started, wherein said synchronous bus request signal is synchronous to said peripheral bus clock signal.
Claim 15
Dependent Claim
39 words
The method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 14 comprising the further step of generating a bus grant signal in response to said synchronous bus request signal.
Claim 16
Dependent Claim
60 words
The method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 14 wherein said step of re-starting said peripheral bus clock signal includes the step of coupling the asynchronous clock request signal from said alternate bus master to a clock control circuit through a control line incorporated on said peripheral bus.
Claim 17
Dependent Claim
37 words
The method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus as recited in Claim 15 wherein said step of generating a bus grant signal is performed by a bus arbiter unit.
Claim 18
Dependent Claim
186 words
A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface and arbiter unit coupled to said local bus and to said peripheral bus for orchestrating the transfer of data and address signals between said local bus and said peripheral bus and for arbitrating mastership of said peripheral bus; a clock generator circuit for providing a peripheral bus clock signal on said peripheral bus, wherein said peripheral bus clock signal is capable of being selectively controlled; a first alternate bus master coupled to said peripheral bus wherein said alternate bus master is capable of asserting a clock request signal when said peripheral bus clock signal is in a power reduction mode; a clock control circuit coupled to said alternate bus master for causing said peripheral bus clock signal to be driven in a normal mode in response to the assertion of said clock request signal; and a second alternate bus master coupled to said peripheral bus; wherein said clock control circuit is capable of providing a clock edge at a selected periodic rate during said power reduction mode.
Claim 19
Dependent Claim
45 words
The computer system as recited in Claim 18 further comprising a latching circuit coupled to receive said clock request signal, wherein said latching circuit provides a synchronous bus request signal to said bus interface and arbiter unit in response to the peripheral bus clock signal.
Claim 20
Dependent Claim
68 words
The computer system as recited in Claim 18 wherein said alternate bus master includes a state machine that asserts said clock request signal when said peripheral bus clock signal is stopped and that asserts a synchronous bus request after said peripheral bus clock signal is re-started, wherein said synchronous bus request signal is provided to said bus interface and arbiter unit for requesting mastership of said peripheral bus.
Claim 21
Dependent Claim
16 words
The computer system as recited in Claim 18 wherein said peripheral bus is a PCI bus.
Claim 22
Dependent Claim
71 words
The computer system as recited in Claim 20 further comprising a power management unit coupled to said clock control circuit and to said clock generator circuit, wherein said power management unit provides a control signal to said clock generator for selectively stopping and re-starting said peripheral bus clock signal, and wherein said clock control circuit provides a command signal to said power management unit in response to said clock request signal.
Claim 23
Dependent Claim
36 words
The computer system as recited in Claim 22 wherein said power management unit stops said peripheral bus clock signal upon the occurrence of a predetermined condition after said microprocessor has attained mastership of said peripheral bus.
Claim 24
Dependent Claim
28 words
The computer system as recited in Claim 20 wherein said bus interface and arbiter unit asserts a bus grant signal in response to said synchronous bus request signal.
Claim 25
Dependent Claim
32 words
The computer system as recited in Claim 20 wherein said peripheral bus includes a control line for coupling said clock request signal from said alternate bus master to said clock control circuit.
Claim 26
Dependent Claim
188 words
A computer system comprising: a microprocessor; a local bus coupled to said microprocessor; a peripheral bus; a bus interface unit coupled to said local bus and to said peripheral bus for orchestrating the transfer of data and address signals between said local bus and said peripheral bus; a clock generator circuit for providing a peripheral bus clock signal on said peripheral bus, wherein said peripheral bus clock signal is capable of being selectively stopped and re-started; a clock control circuit coupled to said clock generator circuit wherein said clock control circuit generates a clock-off control signal to stop said peripheral bus clock signal upon an occurrence of a predetermined condition, and wherein said clock control circuit deasserts a clock request signal at a clock request line prior to generating said clock-off control signal and stopping said peripheral bus clock signal; and a slave device coupled to said peripheral bus, wherein said slave device monitors said clock request line and wherein, if said clock request signal is deasserted, said clock control circuit asserts said clock request signal if said peripheral bus clock signal is required by said slave device.
Claim 27
Dependent Claim
52 words
The computer system as recited in Claim 26 wherein said slave device includes a state machine coupled to said clock request line, wherein said state machine detects the deassertion of said clock request signal and reasserts said clock request signal if said peripheral bus clock signal is required by said slave device.
Claim 28
Dependent Claim
95 words
The computer system as recited in Claim 27 wherein said clock control circuit includes a second state machine, wherein said second state machine deasserts said clock request signal at said clock request line prior to generating said clock-off control signal, and wherein said second state machine delays the generation of said clock-off control signal for a predetermined time if said clock request signal is reasserted by said slave device and does not delay the generation of said clock-off signal for said predetermined time if said clock request signal is not reasserted by said slave device.
Claim 29
Dependent Claim
70 words
The computer system as recited in Claim 26 further comprising an alternate bus master coupled to said peripheral bus wherein said alternate bus master is capable of asserting said clock request signal when said peripheral bus clock signal is stopped, and wherein said clock control circuit generates a clock-on control signal that causes said peripheral bus clock signal to re-start in response to the assertion of the clock request signal.
Claim 30
Dependent Claim
26 words
The computer system as recited in Claim 29 further comprising a bus arbiter unit coupled to said peripheral bus for arbitrating mastership of said peripheral bus.
Claim 31
Dependent Claim
68 words
The computer system as recited in Claim 30 wherein said alternate bus master includes a third state machine that asserts said clock request signal when said peripheral bus clock signal is stopped and that asserts a synchronous bus request signal after said peripheral bus clock signal is re-started, wherein said synchronous bus request signal is provided to said bus arbiter unit for requesting mastership of said peripheral bus.
Claim 32
Dependent Claim
26 words
The computer system as recited in Claim 31 wherein said bus arbiter unit asserts a bus grant signal in response to said synchronous bus request signal.
Claim 33
Dependent Claim
16 words
The computer system as recited in Claim 26 wherein said peripheral bus is a PCI bus.
Claim 34
Dependent Claim
72 words
The computer system as recited in Claim 29 further comprising a power management unit coupled to said clock control circuit and to said clock generator circuit, wherein said power management unit provides a control signal to said clock generator for selectively stopping and re-starting said peripheral bus clock signal, and wherein said clock control circuit provides said clock-on control signal to said power management unit in response to said clock request signal.
Claim 35
Dependent Claim
36 words
The computer system as recited in Claim 34 wherein said power management unit stops said peripheral bus clock signal upon the occurrence of a predetermined condition after said microprocessor has attained mastership of said peripheral bus.
Claim 36
Dependent Claim
19 words
The computer system as recited in Claim 26 wherein said clock request line is incorporated on said peripheral bus.
Claim 37
Independent Claim
124 words
A system for controlling a peripheral bus clock signal comprising: a clock generator for generating said peripheral bus clock signal, wherein said peripheral bus clock signal is capable of being stopped and re-started in response to an ON/OFF signal; a peripheral bus including a clock line for transferring said peripheral bus clock signal; and a clock control circuit coupled to said clock generator, wherein said clock control circuit includes a state machine capable of deasserting said ON/OFF signal to stop said peripheral bus clock signal upon the occurrence of a predetermined condition, and wherein said state machine prevents the deassertion of said ON/OFF signal for a predetermined time if a clock request signal is asserted by a slave device coupled to said peripheral bus.
Claim 38
Dependent Claim
34 words
The system for controlling a peripheral bus clock signal as recited in Claim 37 wherein said state machine of said clock control circuit deasserts said clock request signal prior to deasserting said ON/OFF signal.
Claim 39
Dependent Claim
62 words
The system for controlling a peripheral bus clock signal as recited in claim 38 wherein said state machine of said clock control circuit deasserts said ON/OFF signal to stop said peripheral bus clock signal if said clock request signal is not reasserted by said slave device. within a second predetermined time after said clock request signal is deasserted by said state machine.
Claim 40
Dependent Claim
23 words
The system for controlling a peripheral bus clock signal as recited in Claim 37 wherein said peripheral bus is a PCI standard bus.
Claim 41
Dependent Claim
39 words
The system for controlling a peripheral bus clock signal as recited in Claim 37 further comprising a control line incorporated on said peripheral bus for coupling said clock request signal between said clock control circuit and said slave device.
Claim 42
Independent Claim
111 words
A method for controlling a peripheral bus clock signal comprising the steps of: generating a peripheral bus clock signal within a clock generator; providing said peripheral bus clock signal on a peripheral bus; generating an indicator signal indicative of a decision to stop said peripheral bus clock signal; and if a clock request signal is not asserted by a slave device within a predetermined time after generating said indicator signal, stopping said peripheral bus clock; or if a clock request signal is asserted by said slave device within said predetermined time after generating said indicator signal, keeping on said peripheral bus clock signal for at least a predetermined amount of time.
Claim 43
Dependent Claim
31 words
The method for controlling a peripheral bus clock signal as recited in Claim 42 further comprising the step of providing said indicator signal on a control line of said peripheral bus.
References Cited (Backward Citations)
No citation records indexed.
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