Patent EP0640985A2 successfully refreshed from Google Patents.
EP0640985A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Distributed negative gate power supplies
Assignee: Advanced Micro Devices Inc
•
Filing: 1994-08-03
•
Granted: —
•
Expires: 2014-08-03
Abstract
Abstract A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit (20a, 20b), a plurality of distribution sector pumping means (18a-18p). Each of the plurality of distribution sector pumping circuits is responsive to a half-sector select signal for selectively connecting the primary negative voltage to the wordlines of the selected half-sectors.
Inventors
- 👤 Chung K. Chang
- 👤 Johnny C. Chen
- 👤 Michael A. Van Buskirk
- 👤 Lee E. Cleveland
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 01:58
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C5/00; G11C5/14; G11C5/145
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
126 words
A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure, said distributed negative gate power supply comprising: clock means (22a, 22b) for generating a plurality of clock signals; main charge pumping means (20a, 20b) responsive to an external power supply potential and to said plurality of clock signals for generating a relatively high primary negative voltage; sector logic means (501) for generating half-sector pump select signals, each corresponding to a selected half-sector; and distribution sector pumping means (18a-18p) responsive to said half-sector select signals for selectively connecting said primary negative voltage to the wordlines of the selected half-sectors.
Claim 2
Dependent Claim
126 words
A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure, said distributed negative gate power supply comprising: clock means (22a, 22b) for generating a plurality of clock signals; main charge pumping means (20a, 20b) responsive to an external power supply potential and to said plurality of clock signals for generating a relatively high primary negative voltage; sector logic means (501) for generating half-sector pump select signals, each corresponding to a selected half-sector; and distribution sector pumping means (18a-18p) responsive to said half-sector select signals for selectively connecting said primary negative voltage to the wordlines of the selected half-sectors.
Claim 3
Dependent Claim
36 words
A distributed negative gate power supply as claimed in Claim 1, wherein said distribution sector pumping means is comprised of a plurality of distribution sector pump circuits, each being formed of a relatively small-size, single-stage pump.
Claim 4
Dependent Claim
37 words
A distributed negative gate power supply as claimed in Claim 2, wherein each pump stage is responsive to a secondary high negative voltage associated with said primary negative voltage so as to generate a select control signal.
Claim 5
Dependent Claim
58 words
A distributed negative gate power supply as claimed in Claim 3, wherein said distribution sector pumping means includes a plurality of pass transistors each having its source connected to receive said primary negative voltage, each gate connected to receive said select control signal, and its drain connected to one of said plurality of wordlines in said selected half-sectors.
Claim 6
Dependent Claim
20 words
A distributed negative gate power supply as claimed in Claim 4, wherein said primary negative voltage is approximately -10.5 volts.
Claim 7
Dependent Claim
24 words
A distributed negative gate power supply as claimed in Claim 5, wherein said select control signal has a voltage value of approximately -14 volts.
Claim 8
Dependent Claim
27 words
A distributed negative gate power supply as claimed in Claim 1, wherein said main charge pumping means is formed of a plurality of charge pump stages (301-304).
Claim 9
Dependent Claim
69 words
A distributed negative gate power supply as claimed in Claim 7, further comprising regulation means (24) responsive to said primary high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said main charge pumping means to increase said primary negative voltage or is at a low level so as to decrease said primary negative voltage.
Claim 10
Dependent Claim
57 words
A distributed negative gate power supply as claimed in Claim 1, further comprising means for generating a discharge voltage which is initially pulled up to a small negative voltage so as to allow said primary negative voltage to discharge sufficiently before it is pulled to the external power supply potential thereby avoiding excessive stress on the oxides.
Claim 11
Dependent Claim
146 words
In an array of flash EEPROM memory cells formed on the substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a plurality of bit lines extending along respective columns, a plurality of bit lines extending respective columns, where each memory cell includes an N-type source region coupled to the common source line, a control gate, a floating gate, a channel region and an N-type drain region coupled to a respective one of the bit lines, where each memory cell is erasable predominately by tunneling electrons from its floating gate to its source region, and a distributed negative gate power supply for generating and selectively supplying a relatively high primary negative voltage to control gates of memory cells in selected half-sectors via the wordlines during flash erasure, said distributed negative gate power supply comprising:
Claim 12
Dependent Claim
146 words
In an array of flash EEPROM memory cells formed on the substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a plurality of bit lines extending along respective columns, a plurality of bit lines extending respective columns, where each memory cell includes an N-type source region coupled to the common source line, a control gate, a floating gate, a channel region and an N-type drain region coupled to a respective one of the bit lines, where each memory cell is erasable predominately by tunneling electrons from its floating gate to its source region, and a distributed negative gate power supply for generating and selectively supplying a relatively high primary negative voltage to control gates of memory cells in selected half-sectors via the wordlines during flash erasure, said distributed negative gate power supply comprising:
Claim 13
Dependent Claim
81 words
clock means (22a, 22b) for generating a plurality of clock signals; main charge pumping means (20a, 20b) responsive to an external power supply potential and to said plurality of clock signals for generating a relatively high primary negative voltage; sector logic means (501) for generating half-sector pump select signals, each corresponding to a selected half-sector; and distribution sector pumping means (18a-18p) responsive to said half-sector select signals for selectively connecting said primary negative voltage to the wordlines of the selected half-sectors.
Claim 14
Dependent Claim
81 words
clock means (22a, 22b) for generating a plurality of clock signals; main charge pumping means (20a, 20b) responsive to an external power supply potential and to said plurality of clock signals for generating a relatively high primary negative voltage; sector logic means (501) for generating half-sector pump select signals, each corresponding to a selected half-sector; and distribution sector pumping means (18a-18p) responsive to said half-sector select signals for selectively connecting said primary negative voltage to the wordlines of the selected half-sectors.
Claim 15
Dependent Claim
36 words
A distributed negative gate power supply as claimed in Claim 10, wherein said distribution sector pumping means is comprised of a plurality of distribution sector pump circuits, each being formed of a relatively small-size, single-stage pump.
Claim 16
Dependent Claim
37 words
A distributed negative gate power supply as claimed in Claim 11, wherein each pump stage is responsive to a secondary high negative voltage associated with said primary negative voltage so as to generate a select control signal.
Claim 17
Dependent Claim
58 words
A distributed negative gate power supply as claimed in Claim 12, wherein said distribution sector pumping means includes a plurality of pass transistors each having its source connected to receive said primary negative voltage, each gate connected to receive said select control signal, and its drain connected to one of said plurality of wordlines in said selected half-sector.
Claim 18
Dependent Claim
20 words
A distributed negative gate power supply as claimed in Claim 13, wherein said primary negative voltage is approximately -10.5 volts.
Claim 19
Dependent Claim
24 words
A distributed negative gate power supply as claimed in Claim 14, wherein said select control signal has a voltage value of approximately -14 volts.
Claim 20
Dependent Claim
27 words
A distributed negative gate power supply as claimed in Claim 10, wherein said main charge pumping means is formed of a plurality of charge pump stages (301-304).
Claim 21
Dependent Claim
69 words
A distributed negative gate power supply as claimed in Claim 16, further comprising regulation means (24) responsive to said primary high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow said main charge pumping means to increase said primary negative voltage or is at a low level so as to decrease said primary negative voltage.
Claim 22
Dependent Claim
57 words
A distributed negative gate power supply as claimed in Claim 10, further comprising means for generating a discharge voltage which is initially pulled up to a small negative voltage so as to allow said primary negative voltage to discharge sufficiently before it is pulled to the external power supply potential thereby avoiding excessive stress on the oxides.
Claim 23
Dependent Claim
96 words
A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure, said distributed negative gate power supply comprising: main charge pumping means (22a, 22b) responsive to an external power supply potential (VCC) and to clock signals for generating a relatively high primary negative voltage; and distribution sector pumping means (18a-18p) responsive to half-sector select signals for selectively connecting said primary negative voltage to the wordlines of the selected half-sectors.
Claim 24
Dependent Claim
96 words
A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure, said distributed negative gate power supply comprising: main charge pumping means (22a, 22b) responsive to an external power supply potential (VCC) and to clock signals for generating a relatively high primary negative voltage; and distribution sector pumping means (18a-18p) responsive to half-sector select signals for selectively connecting said primary negative voltage to the wordlines of the selected half-sectors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.