Video format conversion apparatus for high definition television

Claim 2

A video format conversion apparatus for a high definition television according to Claim 1, wherein said decoding means includes: a variable length decoder/demultiplexer circuit for variable length-decoding and demultiplexing the transmitted, encoded signal to separate said video format information, quantized coefficients, a motion vector and a control parameter from the encoded signal; an inverse quantizer for inverse-quantizing the quantized coefficients from said variable-length decoder/demultiplexer circuit in response to the control parameter therefrom; an inverse discrete cosine transform unit for performing an inverse discrete cosine transform with respect to the inverse-quantized coefficients from said inverse quantizer to obtain a displaced frame difference signal based on video motion estimation; a motion compensator for compensating for a motion of a video signal inputted therein using the motion vector from said variable length decoder/demultiplexer circuit; an adder for adding the displaced frame difference signal from said inverse discrete cosine transform unit and the motion-compensated video signal from said motion compensator; a frame memory for storing an output video signal from said adder in the unit of frame and outputting the stored video signal to said motion compensator; and a slice buffer for storing the video signal from said adder in the unit of slice and outputting the stored video signal in the unit of line.

Claim 3

A video format conversion apparatus for a high definition television according to Claim 1, wherein said decimation means includes: switching means for selecting one of the video signals from said decoding means and said frame rate conversion means under the control of said selection control means; vertical decimation means for converting the number of the vertical scanning lines per frame of an output video signal from said switching means into 1050 under the control of said selection control means; and horizontal decimation means for converting the number of pixels per line of an output video signal from said vertical decimation means into that of a 1050-line video format under the control of said selection control means.

Claim 4

A video format conversion apparatus for a high definition television according to Claim 1, wherein said interlaced scanning format conversion/selection means includes: first switching means for selecting one of the video signals from said decoding means, said frame rate conversion means and said decimation means under the control of said selection control means; interlaced scanning format conversion means for converting the scanning format of an output video signal from said first switching means into the interlaced scanning format under the control of said selection control means; and second switching means for selecting one of the video signal from said decoding means and an output video signal from said interlaced scanning format conversion means under the control of said selection control means.

Claim 5

A video format conversion apparatus for a high definition television according to Claim 1, wherein said frame rate conversion means includes: 60Hz frame rate conversion means for converting the frame rate of the video signal from said decoding means into 30Hz under the control of said selection control means if it is 60Hz; 24Hz frame rate conversion means for converting the frame rate of the video signal from said decoding means into 30Hz under the control of said selection control means if it is 24Hz; and multiplexing means for selecting one of output video signals from said 60Hz frame rate conversion means and said 24Hz frame rate conversion means under the control of said selection control means.

Claim 6

A video format conversion apparatus for a high definition television according to Claim 3, wherein said vertical decimation means includes: a first FIFO memory for performing write/read operations with respect to a first one of successive three lines of the video signal from said switching means; a second FIFO memory for performing write/read operations with respect to the video signal from said switching means in the unit of line; an FIFO memory controller for controlling the write and read operations of said first and second FIFO memories under the control of said selection control means; and a multiplexer for selecting alternately output lines from said first and second FIFO memories.

Claim 7

A video format conversion apparatus for a high definition television according to Claim 3, wherein said vertical decimation means includes: a line delay element for delaying the video signal from said switching means in the unit of line; a first FIFO memory for performing write and read operations with respect to a first one of successive three lines of an output video signal from said line delay element; line weighted average calculation means for calculating weighted averages of the lines of the video signals from said switching means and said line delay element according to weighting values under the control of said selection control means; a second FIFO memory for performing write and read operations with respect to an output video signal from said line weighted average calculation means in the unit of line; an FIFO memory controller for controlling the write and read operations of said first and second FIFO memories under the control of said selection control means; and a first multiplexer for selecting alternately output lines from said first and second FIFO memories.

Claim 8

A video format conversion apparatus for a high definition television according to Claim 3, wherein said horizontal decimation means includes: a 1:3-demultiplexer for dividing the video signal from said vertical decimation means into pixels of three phases; a first latch for latching a first one of successive three pixels of the video signal from said vertical decimation means under the control of said selection control means; and a 4:1-multiplexer for selecting alternately output pixels from said 1:3-demultiplexer and said first latch.

Claim 9

A video format conversion apparatus for a high definition television according to Claim 3, wherein said horizontal decimation means includes: a first latch for latching a first one of successive three pixels of the video signal from said vertical decimation means under the control of said selection control means; pixel weighted average calculation means for calculating weighted averages of the pixels of the video signal from said vertical decimation means according to weighting values under the control of said selection control means; a 1:3-demultiplexer for dividing an output video signal from said pixel weighted average calculation means into pixels of three phases; and a 4:1-multiplexer for selecting alternately output pixels from said 1:3-demultiplexer and said first latch.

Claim 10

A video format conversion apparatus for a high definition television according to Claim 4, wherein said interlaced scanning format conversion means includes: line address generation means for generating line addresses under the control of said selection control means to divide each frame into odd and even fields; and a frame memory for storing the video signal from said first switching means in the unit of frame and outputting the stored video signal in the unit of field in response to the line addresses from said line address generation means.

Claim 11

A video format conversion apparatus for a high definition television according to Claim 5, wherein said 60Hz frame rate conversion means includes: an FIFO memory for performing a write operation with respect to the video signal of the 60Hz frame rate from said decoding means, skipping one of two frames at a period of two frame clocks, and a read operation with respect to the stored video signal at a period of twice that of the write operation to output a video signal of the 30Hz frame rate; and an FIFO memory controller for controlling the read and write operations of said FIFO memory under the control of said selection control means to output the video signal of the 30Hz frame rate.

Claim 12

A video format conversion apparatus for a high definition television according to Claim 5, wherein said 24Hz frame rate conversion means includes: an FIFO memory for performing write and read operations with respect to a first one of four frames of the video signal of the 24Hz frame rate from said decoding means at a period of five frame clocks; a frame memory for performing write and read operations with respect to all the four frames of the video signal of the 24Hz frame rate from said decoding means in the unit of frame at the period of the five frame clocks; an FIFO/frame memory controller for controlling the read and write operations of said FIFO memory and said frame memory under the control of said selection control means; and a multiplexer for selecting alternately output frames from said FIFO memory and said frame memory.

Claim 13

A video format conversion apparatus for a high definition television according to Claim 6, wherein said vertical decimation means further includes: filtering means for removing a high frequency component from the video signal from said switching means and outputting the resultant video signal to said first and second FIFO memories.

Claim 14

A video format conversion apparatus for a high definition television according to Claim 7, wherein said line weighted average calculation means includes: a first 1/4 multiplier for multiplying the video signal from said line delay element by 1/4; a first 1/2 multiplier for multiplying the video signal from said line delay element by 1/2; a first adder for adding output signals from said first 1/4 multiplier and said first 1/2 multiplier; a second multiplexer for selecting one of an output signal from said first adder and the output signals from said first 1/4 multiplier and said first 1/2 multiplier under the control of said selection control means; a second 1/2 multiplier for multiplying the video signal from said switching means by 1/2; a second 1/4 multiplier for multiplying the video signal from said switching means by 1/4; a second adder for adding output signals from said second 1/2 multiplier and said second 1/4 multiplier; a third multiplexer for selecting one of an output signal from said second adder and the output signals from said second 1/2 multiplier and said second 1/4 multiplier under the control of said selection control means; and a third adder for adding output signals from said second and third multiplexers.

Claim 15

A video format conversion apparatus for a high definition television according to Claim 8, wherein said horizontal decimation means further includes: filtering means for removing a high frequency component from the video signal from said vertical decimation means and outputting the resultant video signal to said 1:3-demultiplexer and said first latch.

Claim 16

A video format conversion apparatus for a high definition television according to Claim 9, wherein said pixel weighted average calculation means includes: a second latch for latching the video signal from said vertical decimation means; a first 1/4 multiplier for multiplying an output video signal from said second latch by 1/4; a first 1/2 multiplier for multiplying the video signal from said second latch by 1/2; a first adder for adding output signals from said first 1/4 multiplier and said first 1/2 multiplier; a first multiplexer for selecting one of an output signal from said first adder and the output signals from said first 1/4 multiplier and said first 1/2 multiplier under the control of said selection control means; a second 1/2 multiplier for multiplying the video signal from said vertical decimation means by 1/2; a second 1/4 multiplier for multiplying the video signal from said vertical decimation means by 1/4; a second adder for adding output signals from said second 1/2 multiplier and said second 1/4 multiplier; a second multiplexer for selecting one of an output signal from said second adder and the output signals from said second 1/2 multiplier and said second 1/4 multiplier under the control of said selection control means; and a third adder for adding output signals from said first and second multiplexers.

Claim 17

A video format conversion apparatus for a high definition television according to Claim 10, wherein said line address generation means includes: a line counter; a multiplier for multiplying an output signal from said line counter by 2; an adder for adding 1 to an output signal from said multiplier; and a multiplexer for selecting one of the output signal from said multiplier and an output signal from said adder under the control of said selection control means.

Claim 18

A video format conversion apparatus for a high definition television according to Claim 13, wherein said filtering means includes: a plurality of line delay elements connected in series, said line delay elements delaying sequentially the video signal from said switching means in the unit of line and outputting the resultant video signal to said second FIFO memory; a plurality of multipliers, each of said multipliers multiplying a corresponding one of the video signal from said switching means and output signals from said line delay elements by a corresponding one of filtering coefficients; and an adder for adding output signals from said multipliers and outputting the resultant video signal to said first FIFO memory.

Claim 19

A video format conversion apparatus for a high definition television according to Claim 15, wherein said filtering means includes: a plurality of latches connected in series, said latches delaying sequentially the video signal from said vertical decimation means in the unit of pixel and outputting the resultant video signal to said 1:3-demultiplexer; a plurality of multipliers, each of said multipliers multiplying a corresponding one of the video signal from said vertical decimation means and output signals from said latches by a corresponding one of filtering coefficients; and an adder for adding output signals from said multipliers and outputting the resultant video signal to said first latch.