Patent EP0639835A2 successfully refreshed from Google Patents.
EP0639835A2
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Dynamic random access memory device with sense amplifiers serving as cache memory independent of row address buffer unit for high-speed sequential access
Assignee: NEC Corp
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Filing: 1994-08-18
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Granted: —
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Expires: 2014-08-18
Abstract
Abstract A dynamic random access memory device causes sense amplifier circuits (34a/34b/34c/34d) to serve as a cache memory for sequentially delivering data bits in the sense amplifier circuits, and a row address buffer unit (36a) is controlled independently of the sense amplifier circuits (34a/34b/34c/34d) so as to change the row address signal without canceling the data bits in the sense amplifier circuits.
Inventors
- 👤 Sachiko C/O Nec Corporation Kamisaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 20:44
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C11/408; G11C11/4082; G11C11/4091
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
474 words
A dynamic random access memory device having a page mode, comprising: a) a plurality of memory cell arrays (32a/32b/32c/32d) respectively assigned bank addresses (BANK"A"/BANK"B"/BANK"C"/BANK"D") and each implemented by a plurality of memory cells each assigned a row address and a column address; b) a plurality of sets of word lines (WLA1-WLAm/ WLB1-WLBm/ WLC1-WLCm/ WLD1-WLDm) respectively associated with said plurality of memory cell arrays, and each having a plurality of word lines respectively coupled to the rows of memory cells of the associated memory cell array for selectively making said rows of memory cells accessible; c) a plurality of sets of bit line pairs (BLA1-BLAn/ BLB1-BLBn/ BLC1-BLCn/ BLD1-BLDn) respectively associated with said plurality of memory cell arrays, and each having a plurality of bit line pairs respectively coupled to the columns of memory cells for producing potential differences indicative of data bits read out from one of said rows of memory cells; d) a bank addressing system (35a/ 35b) responsive to an external bank address signal for selectively enabling said plurality of memory cell arrays; e) a row addressing system for selecting one of the word lines associated with the memory cell array enabled with said external bank address signal, and having e-1) a row address buffer unit (36a) operative to store an external row address signal indicative of the row address assigned to one of said rows of memory cells incorporated in each memory cell array, e-2) a plurality of row address decoder units (36b/36c) operative to energize one of the word lines coupled to the row of memory cells specified by said external row address signal and incorporated in the memory cell array enabled with said external bank address signal; f) a plurality of sets of sense amplifier circuits (34a/34b/34c/34d) respectively associated with said plurality of sets of bit line pairs, each set of sense amplifier circuits being operative to amplify potential differences on the bit lines of the associated set for storing the potential differences; g) a column addressing system (37a/ 37b/ 37c) responsive to an external column address signal sequentially specifying the column addresses in said page mode for sequentially coupling bit line pairs of the set associated with said memory cell array specified with said external bank address signal to a data bus (DB); h) an interface unit (38) coupled to said data bus, and operative to produce an output data signal (Sout) from the potential difference on said data bus and the potential difference on said data bus from an input data signal (Sin); and i) an internal control signal generating unit (39) responsive to external control signals, and operative to produce a plurality of internal control signals for controlling said page mode, characterized in that each of said plurality of row address decoder units (36b/36c) is shared between two of said plurality of memory cell arrays (32a/32b; 32c/32d).
Claim 2
Dependent Claim
152 words
The dynamic random access memory device as set forth in claim 1, in which said row address buffer unit (36a) is responsive to a first internal control signal (ACT1) of an active level included in said plurality of internal control signals for storing said external row address signal, and cancels said external row address signal in response to said first internal control signal of an inactive level (ACT1), said each set of sense amplifier circuits (34a/34b/34c/34d) being responsive to a second internal control signal (ACT2) of an active level included in said plurality of internal control signals for amplifying said potential differences, said second internal control signal (ACT2) being independent of the change of said first internal control signal (ACT1) so that said row address buffer unit stores said external row address signal indicative of another row address without canceling said potential differences stored in said each set of sense amplifier circuits.
Claim 3
Dependent Claim
77 words
The dynamic random access memory device as set forth in claim 2, in which said internal control signal generating unit (39) has an internal control signal generating circuit (INV31/INV32/ NA31/INV33/ INV34) for producing said first internal control signal (ACT1) from a first external control signal (RAS) and a second external control signal (RSTR), said internal control signal generating circuit being further operative to produce said second internal control signal (ACT2) from said first external control signal (RAS).
Claim 4
Dependent Claim
38 words
The dynamic random access memory device as set forth in claim 3, in which said first external control signal and said second external control signal are a row address strobe signal (RAS) and a restore control signal (RSTR).
Claim 5
Dependent Claim
77 words
The dynamic random access memory device as set forth in claim 3, in which said internal control signal generating circuit comprises a first series combination of logic gates (INV31/INV32) responsive to a row address strobe signal (RAS) for producing said second internal control signal (ACT2), and a second series combination of logic gates (INV31/NA31/INV33/ INV34) enabled with said row address strobe signal (RAS) for producing said first internal control signal (ACT1) from a restore control signal (RSTR).
Claim 6
Dependent Claim
106 words
The dynamic random access memory device as set forth in claim 3, in which said internal control signal generating circuit (INV31/INV32/ NA31/ INV33/INV34)) changes said first internal control signal (ACT1) in response to said second external control signal (RSTR) in the presence of said first external control signal (RAS) of said inactive level for storing the external row address signal, thereby allowing said row addressing system (36a/36b/36c) to select one of the word lines associated with the memory cell array specified by said bank address signal for writing a new data bit into one of the memory cells coupled to said one of said word lines.
Claim 7
Dependent Claim
113 words
The dynamic random access memory device as set forth in claim 2, in which said internal control signal generating unit has a first internal control signal generating circuit (41/NR41/INV41) for producing an internal restore control signal (IRSTR) from a row address strobe signal (RAS) supplied from the outside of said dynamic random access memory device, and a second internal control signal generating circuit (42/43/ NA41/INV42/INV43/ NA42/NA43/NA44) for producing said first internal control signal (ACT1) from said row address strobe signal (RAS) and said internal restore control signal (IRSTR), said second internal control signal generating circuit being further operative to produce said second internal control signal (ACT2) from said row address strobe signal (RAS).
Claim 8
Dependent Claim
177 words
The random access memory device as set forth in claim 2, in which said internal control signal generating unit comprises a first internal control signal generating circuit (41/NR41/INV41) for producing an internal restore control signal (IRSTR) from a row address strobe signal (RAS) supplied from the outside of said dynamic random access memory device, a second internal control signal generating circuit (NR51/NR52) responsive to a write enable signal supplied from the outside of said dynamic random access memory device for changing a third internal control signal (WRITE) to an active level, said second internal control signal generating circuit changing said third internal control signal to an inactive level in response to one of a row address strobe signal (RAS) and said internal restore control signal (IRSTR), and a third internal control signal generating circuit (61/62/NR61/ INV61/INV62/ NA61/63/NA62/ INV63/INV64/NA63/ NA64/INV65/ INV66/ NA65) responsive to said third internal control signal (WRITE), said row address strobe signal (RAS) and said internal restore control signal (IRSTR) for producing said first internal control signal (ACT1) and said second internal control signal (ACT2).
References Cited (Backward Citations)
No citation records indexed.
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