Patent EP0637876A1 successfully refreshed from Google Patents.
EP0637876A1
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EP
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A phase locked loop and method of operation
Assignee: Motorola Solutions Inc
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Filing: 1994-07-14
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Granted: —
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Expires: 2014-07-14
Abstract
Abstract A phase locked loop (22) that generates an output clock signal has a phase/frequency circuit (12), a charge pump circuit (14), a voltage controlled oscillator circuit (16), a first divide-by circuit (24) and a second divide-by circuit (18). The phase/frequency circuit generates a first control signal responsive to a predetermined phase relationship between a first and a second clock signal. The charge pump circuit generates a voltage responsive to the first control signal. The voltage controlled oscillator circuit generates a third clock signal responsive to the voltage. The first and second divide-by circuits serially reduce the frequency of the third clock cycle by a first and a second ratio, respectively. The first ratio is controlled by a second control signal. The output of the first divide-by circuit generates the output clock signal. The output of the second divide-by circuit generates the first clock signal. The phase locked loop has a less onerous VCO bandwidth requirement for a given operating environment and has a reduced phase lock time when changing ratios of input to output clock frequency.
Inventors
- 👤 Hector Sanchez
- 👤 Jose Alvarez
- 👤 Gianfranco Gerosa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:13
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/08; H03L7/085; H03L7/087; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0898
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
206 words
A phase locked loop (22) for generating an output clock signal comprising: a phase/frequency circuit (12) for receiving a first clock signal and a second clock signal, the phase/frequency circuit generating a first control signal responsive to a predetermined phase relationship between the first and second clock signals, the first clock signal characterized by a first frequency, the second clock signal characterized by a second frequency; a charge pump circuit (14) coupled to the phase/frequency circuit, the charge pump circuit generating a voltage responsive to the first control signal; a voltage controlled oscillator circuit (16) coupled to the charge pump circuit, the voltage controlled oscillator circuit generating a third clock signal, the third clock signal characterized by a third frequency, the third frequency responsive to the voltage; a first divide-by circuit (24) coupled to the voltage controlled oscillator circuit, the first divide-by circuit generating an output clock signal, the output clock signal characterized by a fourth frequency, a ratio of the third and fourth frequencies being responsive to a second control signal; and a second divide-by circuit (18) coupled to the first divide-by circuit, the second divide-by circuit generating the first clock signal, the ratio of the first and fourth clock signals being a predetermined ratio.
Claim 2
Independent Claim
164 words
A method of generating an output clock signal comprising the steps of: receiving a first clock signal and a second clock signal at a phase/frequency circuit, the first clock signal characterized by a first frequency, the second clock signal characterized by a second frequency; generating a first control signal at the phase/frequency detector responsive to a predetermined phase relationship between the first and second clock signals; generating a voltage by a charge pump circuit responsive to the first control signal; generating a third clock signal by a voltage controlled oscillator, the third clock signal characterized by a third frequency, the third frequency responsive to the voltage; generating an output clock signal by a first divide-by circuit, the output clock signal characterized by a fourth frequency, a ratio of the third and fourth frequencies being responsive to a second control signal; and generating the first clock signal by a second divide-by circuit, a ratio of the first and the fourth frequencies being a predetermined ratio.
Claim 3
Independent Claim
284 words
A method of generating an output clock signal comprising the steps of: at a first time, receiving a first clock signal and a second clock signal at a phase/frequency circuit, the first clock signal characterized by a first frequency, the second clock signal characterized by a second frequency; generating a first control signal at the phase/frequency detector responsive to a predetermined phase relationship between the first and second clock signals; generating a voltage by a charge pump circuit responsive to the first control signal; generating a third clock signal by a voltage controlled oscillator, the third clock signal characterized by a third frequency, the third frequency responsive to the voltage; generating an output clock signal by a first divide-by circuit, the output clock signal characterized by a fourth frequency, a ratio of the third and fourth frequencies being responsive to a second control signal; generating the first clock signal by a second divide-by circuit, a ratio of the first and fourth frequencies being responsive to a second control signal; and at a subsequent second time, generating the third clock signal by the voltage controlled oscillator, the third clock signal characterized by the third frequency, the third frequency responsive to the voltage, the third frequency at the subsequent second time equal to the third frequency at the first time; generating the output clock signal by the first divide-by circuit, the output clock signal characterized by a fifth frequency, a ratio of the third and fifth frequencies responsive to the second control signal, the fifth frequency different from the fourth frequency; generating the first clock signal by a second divide-by circuit, a ratio of the first and fifth frequencies being responsive to the second control signal.
References Cited (Backward Citations)
EP0072271A1
Cited
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