Patent EP0637035A1 successfully refreshed from Google Patents.
EP0637035A1
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Circuit structure for a memory matrix and corresponding manufacturing method
Assignee: STMicroelectronics SRL
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Filing: 1993-07-29
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Granted: —
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Expires: 2013-07-29
Abstract
Abstract A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL); the bit lines (BL), moreover, are gathered into groups or bytes (9) of simultaneously addressable adjacent lines. Each cell (2) in the matrix incorporates a floating gate transistor (12) which is coupled to a control gate (8), connected to the control gate line (CG), and is connected serially to a selection transistor (5); also, the cells (2) of each individual byte (9) share their respective source areas (6), which areas are structurally independent for each byte (9) and are led to a corresponding source addressing line (SL) extending along a matrix column (7).
Inventors
- 👤 Federico Pio
- 👤 Carlo Riva
- 👤 Silvia C/O Sgs-Thomson Lucherini
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 10:02
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; H10B41/42; H10B41/43; H10B41/47; H10B69/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
148 words
A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells (2) including plural rows (3) and columns (4), with each row (3) being provided with a word line (WL) and a control gate line (CG) and each column (4) having a bit line (BL), said bit lines (BL) being gathered into groups or bytes (9) of simultaneously addressable adjacent lines, and the matrix cells (2) incorporating each a floating gate transistor (12) which is coupled to a control gate (8) connected to the control gate line (CG) and is connected serially to a selection transistor (5), characterized in that: the cells (2) of each individual byte (9) share their respective source areas (6), such areas being structurally independent for each byte (9) and being led to a corresponding source addressing line (SL) extending along a matrix column (7).
Claim 2
Dependent Claim
30 words
A circuit structure according to Claim 1, characterized in that said source addressing line (SL) is split substantially into segments shared by the cells (2) of each individual byte (9).
Claim 3
Dependent Claim
22 words
A circuit structure according to Claim 1, characterized in that said source addressing line is decoded when selecting a desired byte (9).
Claim 4
Dependent Claim
27 words
A circuit structure according to Claim 2, characterized in that each segment (6) is individually addressable, and is decoded when accessing or programming the desired byte (9).
Claim 5
Dependent Claim
39 words
A circuit structure according to Claim 1, characterized in that said source addressing line (SL) comprises at least one enable transistor (A) connected to the source regions (6) of the cells (2) of one and the same byte (9).
Claim 6
Dependent Claim
29 words
A circuit structure according to Claim 5, characterized in that said enable transistor (A) is provided at the crossover of each word line (WL) with the source line (SL).
Claim 7
Dependent Claim
37 words
A circuit structure according to Claim 1, characterized in that said source addressing line (SL) comprises at least a pair of enable transistors (A,B) connected to the source regions (6) of one and the same byte (9).
Claim 8
Dependent Claim
34 words
A circuit structure according to Claim 7, characterized in that the former (A) of said enable transistors (A,B) is provided at the crossover of each word line (WL) with the source addressing line (SL).
Claim 9
Dependent Claim
35 words
A circuit structure according to Claim 7, characterized in that the latter (B) of the enable transistors is provided at the crossover of each control gate (8) line (CG) with the source addressing line (SL).
Claim 10
Independent Claim
97 words
A method for making, in MOS technology, a matrix (1) of memory cells (2) of a type formed, in MOS technology, on a semiconductor substrate (10), the cells (2) comprising floating gate (12) transistors having active source (6) and drain areas and being each connected serially to a respective selection transistor (5), characterized in that it provides for the formation of plural addressing lines (SL) for said active source areas (6) extending along columns (7) of the matrix (1) and each including enable transistors (A,B) formed concurrently with the floating gate transistors and the selection transistors (5).
Claim 11
Dependent Claim
41 words
A method according to Claim 9, characterized in that the active source areas (6) of the transistors incorporated into the cells (2) of a given byte (9) are formed in common with one and the same corresponding source addressing line (SL).
Claim 12
Dependent Claim
38 words
A circuit structure according to Claim 1, characterized in that the source terminals of the transistors incorporated into the cells (2) of a predetermined byte (9) are connected to one and the same corresponding source addressing line (SL).
References Cited (Backward Citations)
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