Patent EP0636976B1 successfully refreshed from Google Patents.
EP0636976B1
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EP
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Microcontroller provided with hardware for supporting debugging as based on boundary scan standard-type extensions
Assignee: Koninklijke Philips NV
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Filing: 1994-07-21
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Granted: 1998-12-30
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Expires: 2014-07-21
Abstract
Abstract A microprocessor comprises a processor element, a memory interface element, an IO interface element, a debug support element and an internal bus interconnecting all above elements. For easy debugging, it also comprises attached to the internal bus a registered boundary scan standard (JTAG) interface that accesses one or more scan chains inside the microprocessor, and is arranged for controlling DMA-type exchanges via the internal bus with other elements connected to this bus. <IMAGE>
Inventors
- 👤 Peter C/O Int. Octrooibureau B.V. Klapproth
- 👤 Frederik C/O Int. Octrooibureau B.V. Zandveld
- 👤 Jacobus M. C/O Int. Octrooibureau B.V. Bakker
- 👤 Gerardus C. C/O Int. Octrooibureau B.V. Van Loo
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:28
CPC Classifications
G; G06; G06F; G06F15/00; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31705; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318572
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
82 words
A microprocessor (20) comprising a processor element (60), a memory interface element (62), an IO interface element, a debug support element (56) and an internal bus (48) interconnecting all above elements, characterized by comprising attached to said internal bus a registered boundary scan standard JTAG interface element (46) that accesses one or more scan chains inside said microprocessor, and furthermore said JTAG interface element is arranged for controlling DMA-type exchanges via said internal bus with other elements connected to said internal bus.
Claim 2
Dependent Claim
24 words
A microprocessor as claimed in Claim 1, wherein said JTAG interface element (46) allows bidirectional downloading informations with respect to an external station (32).
Claim 3
Dependent Claim
29 words
A microprocessor as claimed in Claims 1 or 2, wherein said debug support element (56) is externally to said internal bus (48) directly connected to said processor element (60).
Claim 4
Dependent Claim
23 words
A microprocessor as claimed in Claims 1, 2 or 3, wherein the JTAG interface element (46) directly accesses one or more breakpoint registers.
Claim 5
Dependent Claim
28 words
A microprocessor as claimed in any of Claims 1 to 4, wherein the debug support element (56) directly accesses a trace buffer external (40) to the microprocessor (20).
Claim 6
Dependent Claim
79 words
A microprocessor as claimed in any of Claims I to 5, wherein said debug support element (56) contains an internal buffer memory (58) for accommodating a restricted set of contents of non-sequential addresses as generated by the processing element and allowing at least one of the following storage modes for a limited time operation of said microprocessor: storing of all non-sequential addresses, and/or storing of all call, jump, and trap addresses, or any appropriate selection or part of these.
Claim 7
Dependent Claim
40 words
A microprocessor as claimed in Claim 6, wherein said debug support element (56) interfaces externally to the microprocessor via a serial clocked data path (64) to an external event trace buffer memory (40) for thereto outputting event signalization for storage.
Claim 8
Dependent Claim
25 words
A microprocessor as claimed in Claim 7, wherein a special instruction (WR ASR31) is arranged for controlling loading of said external event trace buffer memory.
Claim 9
Dependent Claim
32 words
A microprocessor as claimed in Claims 7 or 8, wherein the external trace buffer memory (40) is arranged for together with recording any word therein also recording an actual time stamp indication.
Claim 10
Dependent Claim
36 words
A microprocessor as claimed in Claims 7, 8 or 9, wherein the external trace buffer memory (40) is arranged for via a standard further interface outputting data (36) to a standard workstation or personal computer (32).
References Cited (Backward Citations)
No citation records indexed.
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