Patent EP0631269A2 successfully refreshed from Google Patents.
EP0631269A2
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EP
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Liquid crystal driving power supply circuit
Assignee: Toshiba Corp
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Filing: 1994-05-09
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Granted: —
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Expires: 2014-05-09
Abstract
Abstract Five voltage dividing resistors (R1 - R5) are connected in series between the nodes of external power supply voltages (VDD, VEE) to obtain first to fourth divided voltages (V1, V2, V3, V4). A first power amplifier (AMP11) of an Ntop type for impedance conversion is connected to a node (83) of the first voltage (V1). A second power amplifier (AMP12) of a Ptop type for impedance conversion is connected to a node (84) of the second voltage (V2). A third power amplifier (AMP13) of the Ntop type for impedance conversion is connected to a node (85) of the third voltage (V3). A fourth power amplifier (AMP14) of the Ptop type for impedance conversion is connected to a node (86) of the fourth voltage (V4). In each of the first and third power amplifiers (AMP11, AMP13) of the Ntop type, the ability of causing a current to flow out of the amplifier from the output terminal (30) is set to be high, and the ability of causing a current to flow into the amplifier from the output terminal (30) is set to be low. In each of the second and fourth power amplifiers (AMP12, AMP14) of the Ptop type, the ability of causing a current to flow into the amplifier from the output terminal (40) is set to be high, and the ability of causing a current to flow out of the amplifier from the output terminal (40) is set to be low.
Inventors
- 👤 Takeshi C/O Int. Prop. Div. K.K. Toshiba Suyama
- 👤 Shoichi C/O Int. Prop. Div. K.K. Toshiba Iwamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/04; G09G3/16; G09G3/18; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3674; G09G3/3681; G09G3/3685; G09G3/3692; G09G3/3696; G09G2330/00; G09G2330/02
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
231 words
A liquid crystal driving power supply circuit comprising: a first node (81) to which a first power supply voltage (VDD) is applied; a second node (82) to which a second power supply voltage (VEE) is applied; voltage dividing means (R1 - R5) for dividing a voltage between said first and second nodes into a plurality of voltages; first impedance conversion means (AMP12; AMP22), having a first output terminal (40) and an ability of causing a current to flow from the first output terminal to said second node, the ability being set to be higher than an ability of causing a current to flow from said first node to the first output terminal, for receiving a first divided voltage (V2) obtained by said voltage dividing means and outputting a voltage corresponding to the first divided voltage; and second impedance conversion means (AMP13; AMP23), having a second output terminal (30) and an ability of causing a current to flow from said first node to the second output terminal, the ability being set to be higher than an ability of causing a current to flow from the second output terminal to said second node, for receiving a second divided voltage (V3) having a value nearer to the second power supply voltage than the first divided voltage and obtained by said voltage dividing means, and for outputting a voltage corresponding to the second divided voltage.
Claim 2
Dependent Claim
32 words
A circuit according to claim 1, characterized in that said voltage dividing means is constituted by a plurality of resistors (R1 - R5) connected in series between said first and second nodes.
Claim 3
Dependent Claim
134 words
A circuit according to claim 1, characterized in that said first impedance conversion means (AMP12) includes an n-channel MOS transistor (37), having a source, a drain, and a gate and a source-drain path connected between the first output terminal and said second node, for receiving a voltage corresponding to the first divided voltage at the gate, and a first current source (38) connected between said first node and the first output terminal, and said second impedance conversion means (AMP13) includes a p-channel MOS transistor (27), having a source, drain, and gate and a source-drain path connected between said first node and the second output terminal, for receiving a voltage corresponding to the second divided voltage at the gate, and a second current source (28) connected between the second output terminal and said second node.
Claim 4
Dependent Claim
54 words
A circuit according to claim 3, characterized in that the first current source is constituted by a p-channel MOS transistor having a gate to which a predetermined bias voltage is applied, and the second current source is constituted by an n-channel MOS transistor having a gate to which a predetermined bias voltage is applied.
Claim 5
Dependent Claim
218 words
A circuit according to claim 1, characterized in that said first impedance conversion means (AMP12) is constituted by a first differential amplification stage (36) including a p-channel first MOS transistor (33), having a source, a drain, and a gate, for receiving the first divided voltage at the gate, and a first output stage (39) including an n-channel second MOS transistor (37), having a source, a drain, and a gate and a source-drain path connected between the first output terminal and said second node, for receiving an output voltage from said first differential amplification stage at the gate, and a first current source (38) connected between said first node and the first output terminal, and said second impedance conversion means (AMP13) is constituted by a second differential amplification stage (26) including an n-channel third MOS transistor (23), having a source, a drain, and a gate, for receiving the second divided voltage at the gate, and a second output stage (29) including a p-channel fourth MOS transistor (27), having a source, a drain, and a gate and a source-drain path connected between said first node and the second output terminal, for receiving an output voltage from said second differential amplification stage at the gate, and a second current source (28) connected between the second output terminal and said second node.
Claim 6
Dependent Claim
54 words
A circuit according to claim 5, characterized in that the first current source is constituted by a p-channel MOS transistor having a gate to which a predetermined bias voltage is applied, and the second current source is constituted by an n-channel MOS transistor having a gate to which a predetermined bias voltage is applied.
Claim 7
Dependent Claim
342 words
A circuit according to claim 1, characterized in that said first impedance conversion means (AMP12) is constituted by a first differential amplification stage (36) including a p-channel first MOS transistor (33), having a source, a drain, and a gate, for receiving the first divided voltage at the gate, a p-channel second MOS transistor (34) having a source, a drain, and a gate and constituting a first differential pair together with the first MOS transistor, n-channel third and fourth MOS transistors (31, 32) constituting a current mirror load with respect to the first and second MOS transistors, and a first current source (35) for supplying a current to the first differential pair, and a first output stage (39) including an n-channel fifth MOS transistor (37), having a source, drain, and a gate and a source-drain path connected between the first output terminal and said second node, for receiving an output voltage from the first differential amplification stage at the gate, and a second current source (38) connected between said first node and the first output terminal, and said second impedance conversion means (AMP13) is constituted by a second differential amplification stage (26) including an n-channel sixth MOS transistor (23), having a source, a drain, and a gate, for receiving the second divided voltage at the gate, an n-channel seventh MOS transistor (24) having a source, a drain, and a gate and constituting a second differential pair together with the sixth MOS transistor, p-channel eighth and ninth MOS transistors (21, 22) constituting a current mirror load with respect to the sixth and seventh MOS transistors, and a third current source (25) for supplying a current to the second differential pair, and a second output stage (29) including an n-channel tenth MOS transistor (27), having a source, drain, and a gate and a source-drain path connected between the second output terminal and said second node, for receiving an output voltage from the second differential amplification stage at the gate, and a fourth current source (28) connected between said first node and the second output terminal.
Claim 8
Dependent Claim
62 words
A circuit according to claim 7, characterized in that each of the first and second current sources is constituted by a p-channel MOS transistor having a gate to which a predetermined bias voltage is applied, and each of the third and fourth current sources is constituted by an n-channel MOS transistor having a gate to which a predetermined bias voltage is applied.
Claim 9
Dependent Claim
121 words
A circuit according to claim 1, characterized by further comprising: third impedance conversion means (AMP11), having a third output terminal, for receiving a third divided voltage (V1) having a value nearer to the first power supply voltage than the first divided voltage and obtained by said voltage dividing means, and for outputting a voltage corresponding to the third divided voltage from the third output terminal; and fourth impedance conversion means (AMP14), having a fourth output terminal, for receiving a fourth divided voltage (V4) having a value nearer to the second power supply voltage than the second divided voltage and obtained by said voltage dividing means, and for outputting a voltage corresponding to the fourth divided voltage from the fourth output terminal.
Claim 10
Dependent Claim
278 words
A circuit according to claim 9, characterized in that said third impedance conversion means (AMP11) is constituted by a first differential amplification stage (26) including an n-channel first MOS transistor (23), having a source, a drain, and a gate, for receiving the third divided voltage at the gate, an n-channel second MOS transistor (24) having a source, a drain, and a gate and constituting a first differential pair together with the first MOS transistor, p-channel third and fourth MOS transistors (21, 22) constituting a current mirror load with respect to the first and second MOS transistors, and a first current source (25) for supplying a current to the first differential pair, and a first output stage (29) including a p-channel fifth MOS transistor (27), having a source, drain, and a gate and a source-drain path connected between the second output terminal and said second node, for receiving an output voltage from the first differential amplification stage at the gate, and a fourth current source (28) connected between said first node and the third output terminal, and said fourth impedance conversion means (AMP14) is constituted by a second differential amplification stage (36) including a p-channel sixth MOS transistor (33), having a source, a drain, and a gate, for receiving the fourth divided voltage at the gate, a p-channel seventh MOS transistor (34) having a source, a drain, and a gate and constituting a second differential pair together with the sixth MOS transistor, n-channel eighth and ninth MOS transistors (31, 32) constituting a current mirror load with respect to the sixth and seventh MOS transistors, and a second current source (35) for supplying a current to the second differential pair.
Claim 11
Dependent Claim
91 words
A liquid crystal driving power supply circuit comprising: voltage generating means (R1 - R5) for generating a plurality of potentials from the voltage externally applied; and a plurality of impedance conversion means (AMP12, AMP13; AMP22, AMP23) connected to said potentials, respectively, each impedance conversion means having a diving device for driving an output, wherein the driving device of each impedance conversion means is of N type in order to change the output toward a low potential and is of P type in order to change the output toward a high potential.
References Cited (Backward Citations)
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