Patent EP0629956A2 successfully refreshed from Google Patents.
EP0629956A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Bus-to-bus bridge for optimising data transfers between a system bus and a peripheral bus
Assignee: International Business Machines Corp
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Filing: 1994-05-25
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Granted: —
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Expires: 2014-05-25
Abstract
Abstract The present invention provides hardware logic within a host bridge 20 that connects a system bus 36 to a peripheral bus 22 using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The inventive hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.
Inventors
- 👤 Nader Amini
- 👤 Ashu Kohli
- 👤 Gregory N. Santos
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 09:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
95 words
An information handling system (10), comprising: a central processing unit (24); a system bus (36) connected to said central processing unit; a peripheral bus (22) for connecting peripheral devices (18) thereto; a host bridge for connecting said system bus to said peripheral bus; said host bridge (20) including a buffer for temporarily storing data transmitted between said system bus and said peripheral bus; and said host bridge further including a logic network that optimizes the speed at which said data is transmitted into and out of said buffer based upon whether said data is non-contiguous.
Claim 2
Dependent Claim
46 words
An information handling system (10) as claimed in claim 1 wherein said logic network also optimizes the speed at which said data is transmitted into and out of said buffer depending upon an address said data is written into or read from through said system bus.
Claim 3
Dependent Claim
29 words
An information handling system (10) as claimed in claim 2 including increment logic for providing said address said data is written into or read from through said system bus.
Claim 4
Dependent Claim
48 words
An information handling system (10) as claimed in claim 3 wherein said increment logic includes a first adder that increments said address by one address and a second adder that increments said address by two addresses immediately after said data is written or read through said system bus.
Claim 5
Dependent Claim
55 words
An information handling system (10) as claimed in claim 4 wherein said increment logic includes a multiplexor that outputs said incremented address of said first adder or said second adder depending upon whether an address within a burst data transfer should be skipped immediately after said data is written or read through said system bus.
Claim 6
Dependent Claim
18 words
An information handling system (10) as claimed in claim 1 wherein said peripheral bus is a PCI bus.
Claim 7
Dependent Claim
18 words
An information handling system (10) as claimed in claim 1 wherein said peripheral bus is a multiplexed bus.
Claim 8
Dependent Claim
98 words
An information handling system (10), comprising: a central processing unit (24); a system bus (36) connected to said central processing unit; a PCI bus (22) for connecting peripheral devices (18) thereto; a host bridge (20) for connecting said system bus to said PCI bus; said host bridge including a buffer for temporarily storing data transmitted between s aid system bus and said PCI bus; and said host bridge further including a logic network that optimizes the speed at which said data is transmitted into and out of said buffer and through said PCI bus and said system bus.
Claim 9
Dependent Claim
31 words
An information handling system (10) as claimed in claim 8 wherein said logic network includes pacing logic for sensing when a storage space within said buffer is empty of said data.
Claim 10
Dependent Claim
29 words
An information handling system (10) as claimed in claim 9 wherein said pacing logic actuates an enabling signal to a master peripheral device when said storage space is empty.
Claim 11
Dependent Claim
32 words
An information handling system (10) as claimed in claim 10 wherein said master peripheral device writes a string of said data into said storage space when said master receives said enabling signal.
Claim 12
Dependent Claim
27 words
An information handling system (10) as claimed in claim 10 wherein said pacing logic deactuates said enabling signal when said storage space is full of said data.
Claim 13
Dependent Claim
30 words
An information handling system (10) as claimed in claim 9 wherein said pacing logic also is for sensing when said storage space within said buffer is full of said data.
Claim 14
Dependent Claim
32 words
An information handling system (10) as claimed in claim 13 wherein said pacing logic actuates an enabling signal to a master peripheral device when said storage space is full of said data.
Claim 15
Dependent Claim
31 words
An information handling system (10) as claimed in claim 14 wherein said master peripheral device reads said data within said storage space when said master peripheral device receives said enabling signal.
Claim 16
Dependent Claim
105 words
An information handling system (10), comprising: a central processing unit (24); a system bus (36) connected to said central processing unit; a peripheral bus (22) for connecting peripheral devices (18) thereto; a host bridge (20) for connecting said system bus to said peripheral bus; said host bridge including a buffer for temporarily storing data transmitted between said system bus and said peripheral bus; and said host bridge further including logic for prefetching said data into said buffer through said system bus when a master peripheral device connected to said peripheral bus initiates a read burst transfer directed to a slave connected to said system bus.
Claim 17
Dependent Claim
28 words
An information handling system (10) as claimed in claim 16 wherein said logic includes a sensor for detecting when said master peripheral device initiates said read burst transfer.
Claim 18
Dependent Claim
42 words
An information handling system (10) as claimed in claim 16 including a detector for determining when said read burst transfer is complete and actuating a signal to clear said buffer of any data that was not read during said read burst transfer.
Claim 19
Dependent Claim
16 words
An information handling system (10) of claim 16 wherein said peripheral bus is a PCI bus.
Claim 20
Dependent Claim
16 words
An information handling system (10) of claim 16 wherein said peripheral bus is a multiplexed bus.
References Cited (Backward Citations)
No citation records indexed.
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