Radio paging receiver capable of improving accuracy of frame synchronization

Claim 1

A radio paging receiver for use in responding to a pager signal comprising a succession of frames each of which has a frame period and which consists of first through n-th group signals where n represents a positive integer greater than unity, each of said first through said n-th group signals having a signal duration and comprising a call number signal representative of a call number, said radio paging receiver having a preassigned call number which belongs to one of said first through said n-th group signals and comprising receiving means (12) for receiving said pager signal to demodulate said pager signal into a digital signal which comprises a sequence of digital word data, switch means (14) connected between a battery (15) and said receiving means and having on and off states to supply electric power from said battery to said receiving means in said on state, and control means (13) for controlling said switching means to put into said on state during reception of said one of the first through the n-th group signals, characterized in that said control means comprises: first clock generating means (21) for generating a first clock signal having a first clock rate; synchronization clock generating means (22) for generating a synchronization clock signal synchronized with said sequence of digital word data, said synchronization clock signal having a synchronization clock rate equal to said first clock rate; selecting circuit (27) connected to said first clock signal generating means and said synchronization clock generating means for selecting one of said first clock signal and said synchronization clock signal as a selected clock signal; a counter (29) connected to said selecting circuit for counting said frame period by the use of said selected clock signal to produce a counted signal indicative of a beginning and an ending of said one of the first through the n-th group signals; and a control circuit (30) connected to said counter for producing a control signal which lasts from said beginning of the one of the first through the n-th group signals to said ending of the one of the first through the n-th group signals to make said switch means has said on state and to make said synchronization clock generating means generates said synchronization clock signal, said selecting circuit being connected to said control circuit and selecting said synchronization clock signal as said selected clock signal while said control circuit produces said control signal.