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EP0509649A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Selective calling receiver

Assignee: NEC Corp
•
Filing: 1992-03-20
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Granted: —
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Expires: 2012-03-20
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Abstract

Abstract A selective calling receiver includes a decoder having a reference clock oscillator and a CPU having a CPU operating clock oscillator. The decoder includes a timing control circuit for generating a timing signal in synchronism with a synchronizing signal contained in a POCSAG signal and a BCH error correcting circuit for extracting a message code from the POCSAG signal. If the CPU is supplied with a message code from the decoder when no timing signal is inputted from the decoder, the CPU stores the message code in RAM in the CPU or a buffer memory area of external RAM connected to the CPU. In this case, the CPU operates with a first clock signal generated by the reference clock oscillator. When the CPU is supplied with the timing signal from the decoder, the CPU reads the message code from the RAM or the buffer memory area and processes the message code with a second clock signal generated by the CPU operating clock oscillator and the second clock signal has a frequency higher than the frequency of the first clock signal.

Inventors

  • 👤 Motoki C/O Nec Corporation Ide

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 20:47
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0225; H04W52/0229; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H04W88/00; H04W88/02; H04W88/022; Y; Y02; Y02D; Y02D30/00; Y02D30/70

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 191 words
A selective calling receiver for receiving a selective calling signal composed of a plurality of batch signals each having a synchronizing signal and a selective calling code or a message code following said synchronizing signal, comprising: timing signal generating means for extracting said synchronizing signal from said selective calling signal and generating a timing signal in synchronism with said synchronizing signal; message code extracting means for extracting said message code from said selective calling signal; a buffer memory for storing said message code extracted by said message code extracting means; and a microprocessor operable with a first clock signal and a second clock signal having a frequency higher than the frequency of said first clock signal; said microprocessor comprising means for storing said message code into said buffer memory with said first clock signal if said message code is inputted from said message code extracting means when said timing signal is not inputted from said timing signal generating means, and for reading said message code from said buffer memory and processing said message code with said second clock signal when said timing signal is inputted from said timing signal generating means.
Claim 2
Dependent Claim 158 words
A selective calling receiver according to claim 1, wherein a selective calling number of said selective calling receiver is registered in advance, further including decision means for extracting said selective calling code from said selective calling signal, comparing said extracted selective calling code with said selective calling number, and for generating a detected agreement signal when said selective calling code and said selective calling number agree with each other, said microprocessor comprising means for storing said message code into said buffer memory with said first clock signal if said message code is inputted from said message code extracting means when said timing signal is not inputted from said timing signal generating means, and for reading said message code from said buffer memory and processing said message code with said second clock signal when said timing signal is inputted from said timing signal generating means, in the event of application of said detected agreement signal from said decision means.
Claim 3
Dependent Claim 17 words
A selective calling receiver according to claim 2, wherein said selective calling signal comprises a POCSAG signal.
Claim 4
Dependent Claim 39 words
A selective calling receiver according to any one of claims 1 through 3, wherein said buffer memory has a storage capacity for storing a maximum number of bits of said message code contained in one of said batch signals.
Claim 5
Dependent Claim 31 words
A selective calling receiver according to any one of claims 1 through 4, wherein said microprocessor comprises means for processing said message code by converting said message code into character data.
Claim 6
Dependent Claim 17 words
A selective calling receiver according to claim 5, further including display means for displaying said character code.
Claim 7
Dependent Claim 24 words
A selective calling receiver according to any one of claims 1 through 6, further including indicating means for indicating reception of said message code.
Claim 8
Dependent Claim 46 words
A selective calling receiver according to any one of claims 1 through 7, wherein said second clock signal has a frequency high enough for said microprocessor to complete the processing of all message codes stored in said buffer memory within the period of said synchronizing signal.

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