Patent EP0614152A2 successfully refreshed from Google Patents.
EP0614152A2
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EP
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System for optimal electronic debugging and verification employing scheduled cutover of alternative logic simulations
Assignee: International Business Machines Corp
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Filing: 1994-02-14
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Granted: —
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Expires: 2014-02-14
Abstract
Abstract A system for determining the optimal circuit design simulator schedule for debugging a digital electronic circuit design. The system characterizes all available circuit design simulators in terms of several parameters reflecting simulator speed and the time required to discover, isolate and fix a design error (bug). A cutover point is established for any pair of available simulators on the basis of these parameters. One simulator is progressively more efficient than the other beyond this cutover point, which is the desired time for scheduling substitution of the more efficient simulator during the debugging process. The system also permits "what-if" evaluation of alternative debugging strategies in advance by creating alternative schedules in response to various characteristic parameters.
Inventors
- 👤 John David Myers
- 👤 Jose Luis Rivero
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 09:03
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
199 words
A method for debugging a digital electronic circuit design having no more than N bugs that are discoverable in no more than M(N)=M machine cycles of said digital electronic circuit design, each said bug n being discoverable in M(n) machine cycles using a plurality of circuit design simulators {S}, each said simulator S i having an availability fraction h i , having a machine cycle time c i and having an average fix delay time D i between discovery of the n th said bug and correction of said n th bug, wherein i and n are non-zero positive integers, said method comprising the ordered computer-implemented steps of: (a) identifying the number of said machine cycles M(n ci ), corresponding to a cutover bug number n ci for which the debug times are most nearly equal in both of an i th pair of said simulators (S i , S i+1 ); and (b) generating and displaying a debugging schedule for said i th pair of said simulators wherein the predicted discovery time of said critical bug number n ci is specified as the scheduled time for cutover from said simulator S i to said simulator S i+1 .
Claim 2
Dependent Claim
65 words
The method of Claim 1 wherein said identifying step (a) comprises the unordered steps of: (a.1) calculating an exponential coefficient A in accordance with the formula A = ln M/N ; and (a.2) for at least one value of n, calculating said number of machine cycles M(n) required to discover the n th said bug in accordance with the formula M(n) = e A*n .
Claim 3
Dependent Claim
75 words
The method of Claim 2 wherein said identifying step (a) further comprises the step of: (a.3) determining said average fix delay time D i as substantially equivalent to the sum of the average bug isolation time d i and the product of the average time to design and implement a fix f i times the estimated proportion of show-stopping serial bugs s i such that D i = d i +s i *f i .
Claim 4
Dependent Claim
66 words
The method of Claim 3 wherein said identifying step (a) further comprises the step of: (a.4) determining said debug time for the n th said bug as substantially equivalent to the sum of the time required to discover said n th bug (c i *M(n)) and the average fix delay time D i divided by said availability fraction h i such that said debug time equals
Claim 5
Dependent Claim
37 words
The method of Claim 4 wherein said identifying step (a) further comprises the step of: (a.5) identifying said cutover bug number n ci as the sequential bug number most nearly equal to the value of the expression
Claim 6
Dependent Claim
75 words
The method of Claim 1 wherein said identifying step (a) further comprises the step of: (a.1) determining said average fix delay time D i as substantially equivalent to the sum of the average bug isolation time d i and the product of the average time to design and implement a fix f i times the estimated proportion of show-stopping serial bugs s i such that D i = d i +s i *f i .
Claim 7
Dependent Claim
66 words
The method of Claim 6 wherein said identifying step (a) further comprises the step of: (a.2) determining said debug time for the n th said bug as substantially equivalent to the sum of the time required to discover said n th bug (c i *M(n)) and the average fix delay time D i divided by said availability fraction h i such that said debug time equals
Claim 8
Dependent Claim
37 words
The method of Claim 7 wherein said identifying step (a) further comprises the step of: (a.3) identifying said cutover bug number n ci as the sequential bug number most nearly equal to the value of the expression
Claim 9
Independent Claim
210 words
A system for debugging a digital electronic circuit design having no more than N bugs that are discoverable in no more than M(n) = M machine cycles of said digital electronic circuit design, each said bug n being discoverable in M(n) machine cycles using a plurality of circuit design simulators {S}, each said simulator S i having an availability fraction h i , having a machine cycle time c i and having an average fix delay time D i between discovery of the n th said bug and correction of said n th bug, wherein i and n are non-zero positive integers, said system comprising: identification means for identifying the cutover bug number n ci for which the debug times are most nearly equal in both of an i th pair of said simulators (S i , S i+1 ); generation means coupled to said identification means for creating a debugging schedule for said i th pair of said simulators (S i , S i+1 ) wherein the predicted discovery time of said critical bug number n ci is specified as the scheduled time for cutover from said simulator S i to said simulator S i+1 ; and display means coupled to said generation means for displaying said debugging schedule.
References Cited (Backward Citations)
No citation records indexed.
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