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EP0612154A1
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Programmable logic circuit
Assignee: Chancellor Masters & Scholars Of University
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Filing: 1994-02-09
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Granted: —
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Expires: 2014-02-09
Abstract
Abstract A programmable logic device comprises a plurality of logic circuits interconnected through an interconnection network. Each logic circuit comprises an array (14) of memory cells. The memory cells are in a first mode of operation responsive to an address signal at the location of that cell to output data stored in the cell. In a second mode of operation the memory cells are operable to compare data input to it with data stored in it and to output a match signal when said input data matches said stored data. The programmable logic device comprises circuitry for operating that array of memory cells as a random access memory (RAM) with the cells in the first mode of operation and circuitry for operating that array of memory cells as content addressable memory (CAM) in the second mode of operation.
Inventors
- 👤 Anthony Ian Stansfield
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/17796; G; G11; G11C; G11C15/00; G11C15/04; H03K19/17704
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
131 words
A programmable logic device comprising: a plurality of logic elements and connected to each logic element a switch circuit the state of which is controllable to determine connections between the logic elements; a storage circuit providing at least one storage location and operatively connected to the switch circuit; addressing circuitry operatively connected to a plurality of said storage locations whereby a selected one of said storage locations can be addressed, wherein each storage location can be programmed to hold in mode (a) routing data defining the state of its associated switch circuit or in mode (b) logic data representing the result of a logic function and which is output from a selectively addressed storage location; and programming circuitry operable to determine whether the storage circuits implement mode (a) or mode (b).
Claim 2
Dependent Claim
44 words
A programmable logic device as claimed in claim 1, wherein each logic element comprises a logic gate and each switch circuit comprises a selection circuit for selectively connecting from a set of input signals an input signal to an input of said logic gate.
Claim 3
Dependent Claim
26 words
A programmable logic device as claimed in claim 2, wherein each logic gate has a plurality of inputs, with a selection circuit associated with each input.
Claim 4
Dependent Claim
47 words
A programmable logic device as claimed in claim 2 or 3, wherein each logic gate has an output, the outputs of selected logic gates being connected to supply some or all of said set of input signals to the selection circuits of others of said logic gates.
Claim 5
Dependent Claim
29 words
A programmable logic device as claimed in claim 2, 3 or 4, wherein each selection circuit comprises a multiplexer controllable by a data bit stored in said storage location.
Claim 6
Dependent Claim
45 words
A programmable logic device as claimed in claim 1, wherein each logic element is selectively connectable via said switch circuit to an output line of the device, the logic elements being arranged in sets and each set being selectively connectable to a common output line.
Claim 7
Dependent Claim
35 words
A programmable logic device as claimed in claim 6, wherein each logic element is a transistor having its gate connected to receive an input signals and its source/drain path selectively connectable to said output line.
Claim 8
Dependent Claim
145 words
A programmable logic device comprising a plurality of logic circuits interconnected through an interconnection network, each logic circuit comprising: an array of memory cells, each memory cell being (a) responsive to an address signal at the location of that cell to output data stored in the cell, and (b) operable to compare data input to it with data stored in it and to output a match signal when said input data matches said stored data; first circuitry for operating said array as a random access memory (RAM) with the cells in mode a); second circuitry for operating said array as a content addressable memory (CAM) with the cells in mode b); and a mode select circuit operable to selectively control operation of the cell as CAM or RAM, the logic device further comprising programming circuitry arranged to control the state of the mode select circuits.
Claim 9
Dependent Claim
36 words
A programmable logic circuit as claimed in claim 8, wherein the mode select circuit is arranged to route a sequence of data bits input to the cell selectively to one of said first and second circuits.
Claim 10
Dependent Claim
61 words
A programmable logic circuit as claimed in claim 8, wherein the array has a first output for providing output data when it is operating in mode (a) and a second output for providing output data when it is operating in mode (b) and wherein the mode select circuit is arranged to select a particular one of said first and second outputs.
Claim 11
Dependent Claim
98 words
A programmable logic circuit according to claim 8, 9 or 10, wherein the array of memory cells comprises: a plurality of word lines, each word line being connected to a plurality of cells arranged in a row; a plurality of match lines, each match line being arranged to be driven by said plurality of cells in the row; a plurality of data lines, each data line being connected to a plurality of cells arranged in a column; and a plurality of sets of bit lines, each set being connected to a plurality of cells arranged in a column.
Claim 12
Dependent Claim
39 words
A programmable logic circuit according to claim 11, wherein the first circuitry comprises address circuitry for addressing a particular word line of the array and sense circuitry for sensing the data on a particular bit line of the array.
Claim 13
Dependent Claim
37 words
A programmable logic circuit according to any of claims 8 to 12 which includes buffer circuitry connected to inputs and/or outputs of the circuit to enable it to cooperate with neighbouring circuits to form a logic array.
References Cited (Backward Citations)
JPH01125124A
Cited
US5051949A
Cited
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