Patent EP0612151A2 successfully refreshed from Google Patents.
EP0612151A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device capable of reducing a clock skew in a plurality of wiring pattern blocks
Assignee: NEC Corp
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Filing: 1994-02-14
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Granted: —
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Expires: 2014-02-14
Abstract
Abstract In a semiconductor device including a clock driver which provides clock signals, a plurality of electronic elements which are operable in timed relation to the clock signals, provided are a plurality of lattice-shaped wiring blocks to which the electronic elements are connected and each of which has a center portion, and an interconnecting wiring pattern connected to the center portion. The interconnecting wiring pattern connects the clock driver with the center portion of each lattice-shaped wiring block so that a distance between the clock driver and each center portion is substantially equal to one another in the center portions.
Inventors
- 👤 Hitoshi C/O Nec Corporation Okamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 12:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00323; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
92 words
A semiconductor device comprising: a clock driver which provides clock signals having a predetermined frequency; a plurality of lattice-shaped wiring blocks each of which has a center portion; a plurality of electronic elements which are connected to each of said lattice-shaped wiring blocks and which are operable in timed relation to said clock signals; and an interconnecting wiring pattern which connects said clock driver with said center portions so that a distance between said clock driver and each of said center portions is substantially equal to one another in said center portions.
Claim 2
Dependent Claim
30 words
A semiconductor device as claimed in Claim 1, further comprising a plurality of additional wiring patterns through which said electronic elements are connected to each of aid lattice-shaped wiring blocks.
Claim 3
Dependent Claim
25 words
A semiconductor device as claimed in Claim 1, further comprising a plurality of buffer circuits each of which is incorporated in said interconnecting wiring pattern.
Claim 4
Dependent Claim
25 words
A semiconductor device as claimed in Claim 1, further comprising a plurality of buffer circuits each of which is incorporated in said additional wiring patterns.
Claim 5
Dependent Claim
26 words
A semiconductor device as claimed in Claim 1, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has an H-shape.
Claim 6
Dependent Claim
27 words
A semiconductor device as claimed in Claim 1, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has a lattice shape.
Claim 7
Dependent Claim
26 words
A semiconductor device as claimed in Claim 2, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has an H-shape.
Claim 8
Dependent Claim
26 words
A semiconductor device as claimed in Claim 2, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has a lattice-shape.
Claim 9
Dependent Claim
26 words
A semiconductor device as claimed in Claim 3, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has an H-shape.
Claim 10
Dependent Claim
26 words
A semiconductor device as claimed in Claim 3, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has a lattice-shape.
Claim 11
Dependent Claim
26 words
A semiconductor device as claimed in Claim 4, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has an H-shape.
Claim 12
Dependent Claim
26 words
A semiconductor device as claimed in Claim 4, wherein said interconnecting wiring pattern comprises a plurality of subsidiary wiring patterns each of which has a lattice-shape.
References Cited (Backward Citations)
No citation records indexed.
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