Patent EP0610969A2 successfully refreshed from Google Patents.
EP0610969A2
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Active matrix panel
Assignee: Seiko Epson Corp
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Filing: 1989-05-16
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Granted: —
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Expires: 2009-05-16
Abstract
Abstract An active matrix panel comprises a picture element matrix (22), which is mounted on a transparent substrate (71, 86) and which includes a plurality of gate lines (24, 25), a plurality of source lines (26, 27, 28) and a plurality of picture elements (32, 33). Each of the picture elements includes a thin film transistor (29, 101). The active matrix panel further includes a gate line drive circuit (21) and a source line drive circuit (12) and being characterised in that at least one of the gate line drive circuit and the source line drive circuit comprises a plurality of complementary thin film transistors (47 to 56; 58, 59; 99, 100) provided on the transparent substrate. The complementary thin film transistors comprise a P type thin film transistor including acceptor impurities in the source region and the drain region thereof and an N type thin film transistor including acceptor impurities and donor impurities in the source region and the drain region thereof, the donor impurities in the N type thin film transistor having a higher concentration than the acceptor impurities in the n type thin film transistor.
Inventors
- 👤 Toshiyuki Misawa
- 👤 Hiroyuki Oshima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 12:24
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; G09; G09G; G09G3/00; G09G3/001; G09G3/002; G09G3/003; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3674; G09G3/3677; G09G3/3685; G09G3/3688; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D86/00; H10D86/40; H10D86/441; H10D86/60; H10W; H10W20/00; H10W20/40; G02F1/133345; G02F1/136; G02F1/1362; G02F1/136213; G02F1/136254; G09G2300/00; G09G2300/04; G09G2300/0404; G09G2300/0408; G09G2300/08; G09G2300/0809; G09G2330/00; G09G2330/12; G09G3/006; G09G3/2007; G09G3/2011; G09G3/3659; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10W72/00; H10W72/01; H10W72/015; H10W72/01515; H10W72/071; H10W72/075; Y; Y10; Y10S; Y10S257/00; Y10S257/923; Y10S345/00; Y10S345/904
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
190 words
An active matrix panel comprising a picture element matrix (22), which is mounted on a transparent substrate (71, 86) and which includes a plurality of gate fines (24, 25), a plurality of source lines (26, 27, 28) and a plurality of picture elements (32, 33), each of the picture elements including a thin film transistor (29, 101), the active matrix panel further comprising a gate line drive circuit (21) and a source line drive circuit (12) and being characterised in that at least one of the gate line drive circuit and the source line drive circuit comprises a plurality of complementary thin film transistors (47 to 56; 58, 59; 99, 100) provided on the transparent substrate, and in that the complementary thin film transistors comprise a P type thin film transistor including acceptor impurities in the source region and the drain region thereof and an N type thin film transistor including acceptor impurities and donor impurities in the source region ad the drain region thereof, the donor impurities in the N type thin film transistor having a higher concentration than the acceptor impurities in the n type thin film transistor.
Claim 2
Dependent Claim
190 words
An active matrix panel comprising a picture element matrix (22), which is mounted on a transparent substrate (71, 86) and which includes a plurality of gate lines (24, 25), a plurality of source lines (26, 27, 28) and a plurality of picture elements (32, 33), each of the picture elements including a thin film transistor (29, 101), the active matrix panel further comprising a gate line drive circuit (21) and a source line drive circuit (12) and being characterised in that at least one of the gate line drive circuit and the source line drive circuit comprises a plurality of complementary thin film transistors (47 to 56; 58, 59; 99, 100) provided on the transparent substrate and in that the complementary thin film transistors comprise an N type thin film transistor including donor impurities in the source region and the drain region thereof and a P type thin film transistor including donor impurities and acceptor impurities in the source region and the drain region thereof, the acceptor impurities in the P type thin film transistor having a higher concentration than the donor impurities in the P type thin film transistor.
Claim 3
Independent Claim
201 words
A method of manufacturing a complementary TFT integrated circuit for an active matrix panel comprising the steps of: forming a desired pattern after accumulating a layer of silicon thin film over a transparent insulating substrate (110) thereby forming a channel region (111) of a P type TFT and channel regions (112, 113) of N type TFTs; forming gate insulating film regions (114, 115, 116) by means of thermal oxidation or chemical vapour deposition, and then forming gate electrodes (117, 118, 119); implanting acceptor impurities (120) over the surface utilising ion implantation techniques in first regions (121, 122) and second regions (123, 124, 125 and 126) then; covering the P type TFTs by a masking material and implanting donor impurities (127) elsewhere with a higher concentration than that of the acceptor impurities (120) and activating implanted donor impurities in the first regions (121, 122) and second regions (123, 124, 125, 126) by subsequent heat treatment, thus forming source/drain regions (123, 124, 125, 126) of P type and N type TFTs respectively, then; accumulating an insulating film layer (129) after removing the mask material (128) opening through holes, forming a picture element electrode (131) of transparent conductive film and forming a line (130).
Claim 4
Independent Claim
205 words
A method of manufacturing a complementary TFT integrated circuit for an active matrix panel comprising the steps of: forming a desired pattern after accumulating a layer of silicon thin film over a transparent insulating substrate (110) thereby forming a channel region (111) of an N type TFT (132) and channel regions (112, 113) of P type TFTs (133, 134); forming gate insulating film regions (114, 115, 116) by means of thermal oxidation or chemical vapour deposition, and then forming gate electrodes (117, 118, 119); implanting donor impurities (127) over the surface utilising ion implantation techniques in first regions (121, 122) and second regions (123, 124, 125 and 126), then; covering the N type TFTs by a masking material and implanting acceptor impurities (120) elsewhere with a higher concentration than that of the donor impurities (127) and activating implanted acceptor impurities in the first regions (121, 122) and the second regions (123, 124, 125, 126) by subsequent heat treatment, thus forming source/drain regions (123, 124, 125, 126) of N type and P type TFTs respectively, then; accumulating an insulating film layer (129) after removing the mask material (128) opening through holes, forming a picture element electrode (131) of transparent conductive film and forming a line (130).
References Cited (Backward Citations)
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