Patent EP0606758B1 successfully refreshed from Google Patents.
EP0606758B1
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EP
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Method of producing an SOI transistor DRAM
Assignee: Samsung Electronics Co Ltd
•
Filing: 1993-12-23
•
Granted: 2000-09-06
•
Expires: 2013-12-23
Abstract
No abstract record available.
Inventors
- 👤 Kyucharn Park
- 👤 Yeseung Lee
- 👤 Cheonsu Ban
- 👤 Kyungwook Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:38
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/036; H10B12/30; H10B12/33
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
227 words
A method for making a dynamic random access memory
comprising the steps of: recessing a cell area of a lower surface of a silicon substrate (1)
by a first depth, wherein the substrate has the lower
surface and an upper surface opposite the lower surface, and
the lower surface is divided into the cell area where a
memory device is formed and a peripheral area; forming a trench having a bottom area and a sidewall
into the recessed cell area; forming a first insulating layer (3) over the lower
surface; forming a contact hole in the first insulating layer; depositing and patterning a first conductive layer (5, 7) to
form a storage node (6) in contact with the lower surface of the
substrate through the contact hole; forming a dielectric layer on the storage node; forming a second conductive layer on the dielectric
layer to form a plate node (9); planarizing the lower surface of the substrate;
polishing the upper surface
to
expose the first insulating layer filled in the trench such
that a portion of the upper surface opposite the cell area
has a thin silicon-on-insulator layer surrounded by the
trench and a portion of the upper surface opposite the
peripheral area has a thick silicon-on-insulator layer; and forming a switching element on the upper surface of the
thin silicon-on-insulator layer and the thick silicon-on-insulator
layer.
Claim 2
Dependent Claim
53 words
The method according to Claim 1, wherein the step of
depositing and patterning the first conductive layer
comprises the substeps of: forming an undoped polysilicon layer (5) over the
lower surface in contact with the lower surface throughout
the contact hole; and forming a doped polysilicon layer (7) over the undoped
polysilicon layer.
Claim 3
Dependent Claim
32 words
The method of Claim 1, wherein the first depth is
greater than the combined thickness of the first insulating
layer, the first conductive layer, the dielectric layer, and
the second conductive layer.
Claim 4
Dependent Claim
26 words
The method of Claim 3, further comprising the step of
bonding a handling wafer (15) to the planarized lower surface
prior to polishing the upper surface.
Claim 5
Dependent Claim
22 words
The method of Claim 1, further comprising the step of
forming a planarizing layer before planarizing the lower
surface of the substrate.
Claim 6
Dependent Claim
200 words
A method for making a dynamic random access memory as
claimed in Claim 1, comprising: forming a well on the lower surface of said silicon substrate (1);
filling the trench with buried oxide (105); forming a buried
contact (108) on said buried oxide; forming a capacitor;
planarizing a pattern formed by said processes; bonding the
lower surface of the substrate (1) to a second substrate (15) forming
a handling wafer; removing silicon to the bottom of said
trench; wet-etching a silicon layer formed on an area that
is not recessed on said silicon substrate and performing
isolation of electrical elements by means of a local
oxidation of silicon process; forming devices of a
peripheral circuit such as n-type and p-type metal oxide
semiconductors and a register pattern in a conventional
manner; forming devices such as a metal oxide semiconductor
and a transistor on the recessed area of said silicon
substrate; forming contacts simultaneously on a plate node,
a cell, a gate and a metallization of the peripheral circuit
and on a bit line, respectively; forming simultaneously a
bit line (127) of the cell area and the metallization of the
peripheral circuit; and carrying out passivation and
alloying on said pattern.
Claim 7
Dependent Claim
22 words
The method according to Claim 6, wherein the step of
recessing the silicon to the bottom of said trench follows
lapping/wet-etching/chemical-and-mechanical polishing.
Claim 8
Dependent Claim
28 words
The method according to Claim 6 or 7, wherein an
etchstopping layer is formed so as to facilitate said
lapping/wet-etching/chemical-and-mechanical polishing
process prior to recessing the specified area.
Claim 9
Independent Claim
29 words
The method according to any one of Claims 6 to 8,
wherein an etchstopping layer is formed so as to facilitate
recessing the specified area prior to said process.
Claim 10
Independent Claim
31 words
The method according to any one of Claims 6 to 9,
wherein said planarization process includes a chemical-and-mechanical
polishing process after applying a buried oxide
and overlaying polysilicon or amorphous silicon.
Claim 11
Independent Claim
31 words
The method according to any one of Claims 6 to 10,
wherein the lower surface of the substrate is bonded to the
handling wafer after an SiO 2 layer is formed.
Claim 12
Independent Claim
43 words
The method according to any one of Claims 6 to 11,
wherein the bonding process to the handling wafer is carried
out by successively and thermally treating in an ambient of
0 2 after thermal treatment in an ambient of N 2 .
Claim 13
Independent Claim
34 words
The method according to any one of Claims 6 to 11,
wherein a gate electrode of said metal oxide semiconductor
in the cell area and the line of the peripheral circuit are
simultaneously formed.
Claim 14
Independent Claim
78 words
The method according to any one of Claims 6 to 11,
wherein isolation of electrical elements using a local
oxidation of silicon process is performed by making devices
of the peripheral area and applying an interlayer insulating
layer after covering a silicon oxide layer/silicon nitride
layer/silicon oxide layer on a specified area including the
cell, and then carrying out a planarization in a chemical-mechanical
polishing method, using the silicon nitride layer
of a predetermined area as a stopper.
Claim 15
Independent Claim
33 words
The method according to any one of Claims 6 to 14,
wherein said process for making the capacitor a plate node
of said capacitor penetrates between the buried oxide and
the storage node.
References Cited (Backward Citations)
No citation records indexed.
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