EP0606643A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method and system for nonsequential instruction dispatch and execution in a superscalar processor system
Assignee: International Business Machines Corp
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Filing: 1993-12-27
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Granted: —
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Expires: 2013-12-27
Abstract
Abstract A method and system for permitting nonsequential instruction dispatch in a superscalar processor system. A plurality of intermediate storage buffers (40,42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40,42) is assigned to any destination operand within the dispatched instruction, permitting the results of the execution of each instruction to be stored within an intermediate storage buffer (40,42). An indication of the status of each instruction is maintained within a completion buffer (48) and thereafter utilized to selectively transfer results within the intermediate storage buffers (40,42) to selected general purpose registers (44,46) in an ordered consistent with an application specified sequential order. The occurrence of an interrupt which prohibits completion of a selected instruction can therefore be accurately identified within the completion buffer (48).
Inventors
- 👤 James A. Kahle
- 👤 Donald E. Waldecker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 09:52
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
166 words
A method for enhanced instruction dispatch efficiency in a superscalar processor system (10) capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of said scalar instructions to a plurality of execution units (24), said method comprising the steps of: dispatching (80-94) selected ones of said group of scalar instructions to selected ones of said plurality of execution units (24) on an opportunistic basis; storing results of execution of each of said dispatched scalar instructions in intermediate storage buffers (60) within said superscalar processor system (10); maintaining (120-132) an indication of completion of execution of each of said dispatched scalar instructions in a completion buffer (48); and transferring (136) results of execution of selected ones of said dispatched scalar instructions from said intermediate storage buffers (60) to selected general purpose registers (62) in an order consistent with said application specified ordered sequence in response to an indication of completion of execution of said selected ones of said dispatched scalar instructions.
Claim 2
Dependent Claim
64 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 1, wherein said step of maintaining (120-132) an indication of completion of execution of each of said dispatched scalar instructions in a completion buffer (48) further comprises maintaining an indication of an exception occurrence during execution of any of said dispatch scalar instructions in said completion buffer (48).
Claim 3
Dependent Claim
124 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 2, wherein said step of transferring (136) results of execution of selected ones of said dispatch scalar instructions from said intermediate storage buffers (60) to said selected general purpose registers (62) in an order consistent with said application specified ordered sequence in response to an indication of completion of execution of said selected ones of said dispatch scalar instructions further comprises the step of transferring (127-128) results of execution of only those dispatch scalar instructions which precede said exception occurrence in said application specified ordered sequence to selected general purpose registers (62) in an order consistent with said application specified ordered sequence in response to said exception occurrence.
Claim 4
Dependent Claim
36 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 3, further including the step of identifying (126) a particular one of said scalar instructions which initiated said exception occurrence.
Claim 5
Dependent Claim
40 words
The method for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 4, further including the step of restarting (130) said application at said particular one of said scalar instructions after correction of said exception occurrence.
Claim 6
Independent Claim
171 words
A system for enhanced instruction dispatch efficiency in a superscalar processor system (10) capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of said scalar instructions to a plurality of execution units (24), said system comprising: means for dispatching (80-94) selected ones of said group of scalar instructions to selected ones of said plurality of execution units (24) on an opportunistic basis; means for storing results of execution of each of said dispatched scalar instructions in intermediate storage buffers (60) within said superscalar processor system (10); means for maintaining (120-132) an indication of completion of execution of each of said dispatched scalar instructions in a completion buffer (48); and means for transferring (136) results of execution of selected ones of said dispatched scalar instructions from said intermediate storage buffers (60) to selected general purpose registers (62) in an order consistent with said application specified ordered sequence in response to an indication of completion of execution of said selected ones of said dispatched scalar instructions.
Claim 7
Dependent Claim
66 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 6, wherein said means for maintaining (120-132) an indication of completion of execution of each of said dispatched scalar instructions in a completion buffer (48) further comprises means for maintaining an indication of an exception occurrence during execution of any of said dispatch scalar instructions in said completion buffer (48).
Claim 8
Dependent Claim
123 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 2, wherein said means for transferring (136) results of execution of selected ones of said dispatch scalar instructions from said intermediate storage buffers (60) to said selected general purpose registers (62) in an order consistent with said application specified ordered sequence in response to an indication of completion of execution of said selected ones of said dispatch scalar instructions further comprises means for transferring (127-128) results of execution of only those dispatch scalar instructions which precede said exception occurrence in said application specified ordered sequence to selected general purpose registers (62) in an order consistent with said application specified ordered sequence in response to said exception occurrence.
Claim 9
Dependent Claim
35 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 8, further including means for identifying (126) a particular one of said scalar instructions which initiated said exception occurrence.
Claim 10
Dependent Claim
39 words
The system for enhanced instruction dispatch efficiency in a superscalar processor system (10) according to Claim 9, further including means for restarting (130) said application at said particular one of said scalar instructions after correction of said exception occurrence.
References Cited (Backward Citations)
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