Synchronous LSI memory device

Claim 2

The synchronous LSI memory device of claim 1, which further comprises first means (SHIFT REGISTER) operative in response to the second signal (CP) to control access to said memory cell array means (BK1, BK2).

Claim 3

The synchronous LSI memory device of claim 2, wherein said first means (SHIFT REGISTER) has the number of bits even-number times larger than that obtained during a cycle interval during which a column address is inputted, for activating column systems (COL SYS) of said memory cell array means (BK1, BK2) on the basis of specific output signals (K) of said first means (SHIFT REGISTER).

Claim 4

The synchronous LSI memory device of claim 2, wherein said first means (SHIFT REGISTER) comprises two-set independent shift registers (SHIFT 1, 2).

Claim 5

The synchronous LSI memory device of claim 2, wherein said first means (SHIFT REGISTER) changes an initial condition according to read latency.

Claim 6

A synchronous LSI memory device, comprising: cell block means (CB) each having a plurality of memory cells; and data register means (WRITE REGISTER) for acquiring externally input data applied to first terminals (DQ) in synchronism with a clock signal (CLK), said data register means being provided with inputting registers (WRITE REGISTER) having a plurality of bits and connected to the respective first terminals; and when data are inputted, the inputting registers being controlled so that the respective plural bits are switched in sequence or not controlled so that the respective plural bits are set alternately to data input status.

Claim 7

A synchronous LSI memory device, comprising: memory cell array means (BK1, BK2) each having a plurality of memory cells; timing generating means (TG) for generating a first basic signal (CPOR) synchronous with a clock signal (CLK) and masked according to status of a control signal (CKE); signal generating means (SERIAL SYS CONTROL) for generating a second signal (CP) in synchronism with the first basic signal (CPOR) and stopping generating the second signal (CP) after a predetermined number of accesses or in response to a stop signal (MRRST, MWSTP LADA, BSTP); control means for controlling said cell array means (BK1, BK2) on the basis of outputs of said timing signal generating means and said signal generating means (SERIAL SYS CONTROL); and mask control means (DQMR) for acquiring statuses of second terminals (DQM) in sequence into register means having the number of bits even-number times larger than that obtained during a cycle interval during which a column address is inputted, outputting the acquired data in sequence, inputting the outputted data, respectively to specific registers each having the number of bits even-number times larger than that obtained during the cycle interval during which the column address is inputted, and when data inputted through the second terminals (DQM) are in a first status, outputting signals for setting output circuits of the register means to a high impedance status in synchronism with the second signal (CP).

Claim 8

The synchronous LSI memory device of claim 7, which further comprises: data holding means (DQM WRITE REGISTER) for, in only write mode, acquiring the statuses of the second terminals (DQM) in synchronism with the second signal into registers having a plurality of bits in sequence and scrambling the acquired data on first data lines (DQMW) plural bits by plural bits every plural cycles; and precharge means (EQDQM) for precharging the first data lines into write disable status every predetermined cycle interval.

Claim 9

The synchronous LSI memory device of claim 8, wherein when the predetermined access length is "1", even-number registers of said data holding means (DQM WRITE REGISTER) are fixed to status the same as when masked data are acquired.

Claim 10

The synchronous LSI memory device of claim 7, which further comprises: read mask registers (DQM READ REGISTER) for acquiring, in read mode, the statuses of the second terminals (DQM) into a plurality of registers in sequence in synchronism with the second signal, and outputting the acquired data to the data lines (DQMR) in sequence; and potential fixing means (/RPRM13, /RPRM24, HIZ) for fixing, in write mode, potentials of the data lines (DQMR) to set the output circuits connected to the data lines (DQMR) to a high impedance status.

Claim 11

The synchronous LSI memory device of claim 10, wherein when the predetermined access length is "1", even-number registers of said read mask registers having a bit number length half of a word length are fixed to a mask data output status.

Claim 12

The synchronous LSI memory device of claim 1, wherein the stop signal (CLADA) is outputted subsequent to a predetermined number of accesses after all banks (BK1, BK2) have been precharged.

Claim 13

The synchronous LSI memory device of claim 12, wherein when the write latency is "1", the stop signal (WRLA) is outputted in a first cycle immediately after write disable mode has been changed to write enable mode.

Claim 14

The synchronous LSI memory device of claim 1, wherein the number of predetermined accesses is counted on the basis of a signal (REG1, REG2) for selecting bits n-bits by n-bits by interleaving an m(= n + n)-bit register having two sets of n-bit registers.

Claim 15

The synchronous LSI memory device of claim 1, wherein when a plurality of said cell block (CB) are accessed in series, a plurality of serially accessed cell blocks can be accessed simultaneously.

Claim 16

The synchronous LSI memory device of claim 15, wherein when a plurality of said cell array means are accessed simultaneously, data buffers whose number is a half of that required when a single cell array is accessed are activated in the respective cell arrays means.

Claim 17

The synchronous LSI memory device of claim 1, wherein the second signal (CP) is divided into a plurality of signals (CPK, CPW, CPR) according to use so as to be controlled individually.