Line accommodation circuit

Claim 1

A line accommodation circuit supplied with a sequence of input data signals to supply a sequence of output asynchronous transfer mode cells to a cell exchange apparatus, said line accommodation circuit comprising a first function system which is operated as an active system and a second function system which is identical in structure with said first function system and is operated as a standby system, said input data signal sequence being synchronously sent to both the active and the standby systems, each of said first and said second function systems comprising: a system controller for carrying out a switching operation between said active and said standby systems to render said first and said second function systems into a new standby system and a new active system, respectively; a controllable cell processor controlled by said system controller for successively carrying out. under control of said system controller, a conversion operation of said input data signals into internal asynchronous transfer mode cells corresponding to said output asynchronous transfer mode cells; a cell insertion circuit coupled to said system controller for producing, under control of said system controller, a predetermined cell distinguished from said internal asynchronous transfer mode cells; an input buffer coupled to said system controller for storing said internal asynchronous transfer mode cells and said predetermined cell to produce said internal asynchronous transfer mode cells and said predetermined cell as stored asynchronous transfer mode cells and a stored predetermined cell, respectively, under control of said system controller; a cell detector coupled to said system controller and said input buffer for detecting said stored predetermined cell to supply a detection signal to said system controller on detection of said stored predetermined cell and, otherwise, to allow said stored asynchronous transfer mode cells to pass therethrough under control of said system controller; and an output circuit coupled to said system controller and said cell detector for producing said stored asynchronous transfer mode cells as said output asynchronous transfer mode cells under control of said system controller; the active system being controlled on said switching operation by said system controller so that the cell processor in the active system stops said conversion operation during said switching operation while the cell insertion circuit in said active system produces said predetermined cell after a last one of the internal asynchronous transfer mode cells that is left in said cell processor of the active system is sent to the input buffer in said active system; the standby system being controlled on said switching operation by said system controller so that the cell processor in the standby system starts the conversion operation after said predetermined cell is sent from said cell insertion circuit to said input buffer in the standby system, to store, in said input buffer of the standby system, a following one of the internal asynchronous transfer mode cells that succeeds said last one of the asynchronous transfer mode cells, with said following one of the internal asynchronous transfer mode cells preceded by said predetermined cell in the input buffer of the standby system.

Claim 9

A method of converting a sequence of data input signals into a sequence of asynchronous transfer mode cells in a line accommodation circuit, comprising supplying the input signals synchronously and in parallel to two functionally-identical conversion systems, one of which is in an active mode and the other is in a standby mode; converting the input signals into the sequence of transfer mode cells in the active system; monitoring the operation of the active system and in the event of a defect sending to both the active and the standby systems a predetermined cell distinguishable from the transfer mode cells; stopping conversion of further data input signals by the active system upon receipt thereby of the predetermined cell and inserting the predetermined cell into the active system immediately following the last transfer mode cell therein; starting conversion of the data input signals into transfer mode cells by the standby system upon receipt thereby of the predetermined cell and inserting the predetermined cell into the standby system immediately preceding the first converted transfer mode cell therein, said first transfer mode cell being converted from the data input signal immediately following the data input signal converted to the said last transfer mode cell; detecting the predetermined cells in the active and standby systems; and upon said detection switching the standby system into the active mode, and the active system into the standby mode.